clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
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@ -14,6 +14,21 @@ Required Properties:
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- #clock-cells: should be 1.
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- clocks:
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- pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
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is used if not specified.
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- pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
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is used if not specified.
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- cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
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specified.
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- sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
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not specified.
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- sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
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specified.
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- clock-names: Aliases for the above clocks. They should be "pll_ref",
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"pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume. Some of the clocks are available only on a particular
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@ -35,7 +50,8 @@ sclk_i2s 7
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pcm_bus 8
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sclk_pcm 9
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Example 1: An example of a clock controller node is listed below.
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Example 1: An example of a clock controller node using the default input
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clock names is listed below.
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5250-audss-clock";
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@ -43,7 +59,19 @@ clock_audss: audss-clock-controller@3810000 {
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#clock-cells = <1>;
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};
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Example 2: I2S controller node that consumes the clock generated by the clock
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Example 2: An example of a clock controller node with the input clocks
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specified.
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5250-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
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<&ext_i2s_clk>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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};
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Example 3: I2S controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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@ -28,10 +28,6 @@ static struct clk_onecell_data clk_data;
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#define ASS_CLK_DIV 0x4
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#define ASS_CLK_GATE 0x8
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/* list of all parent clock list */
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static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
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static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
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#ifdef CONFIG_PM_SLEEP
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static unsigned long reg_save[][2] = {
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{ASS_CLK_SRC, 0},
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@ -68,6 +64,10 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
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{
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int i, ret = 0;
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struct resource *res;
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const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
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const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
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const char *sclk_pcm_p = "sclk_pcm0";
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struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg_base = devm_ioremap_resource(&pdev->dev, res);
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@ -85,11 +85,23 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
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clk_data.clks = clk_table;
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clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
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pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
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pll_in = devm_clk_get(&pdev->dev, "pll_in");
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if (!IS_ERR(pll_ref))
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mout_audss_p[0] = __clk_get_name(pll_ref);
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if (!IS_ERR(pll_in))
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mout_audss_p[1] = __clk_get_name(pll_in);
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clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
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mout_audss_p, ARRAY_SIZE(mout_audss_p),
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CLK_SET_RATE_NO_REPARENT,
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reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
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cdclk = devm_clk_get(&pdev->dev, "cdclk");
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sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
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if (!IS_ERR(cdclk))
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mout_i2s_p[1] = __clk_get_name(cdclk);
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if (!IS_ERR(sclk_audio))
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mout_i2s_p[2] = __clk_get_name(sclk_audio);
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clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
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mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
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CLK_SET_RATE_NO_REPARENT,
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@ -123,8 +135,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
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"sclk_pcm", CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 4, 0, &lock);
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sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
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if (!IS_ERR(sclk_pcm_in))
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sclk_pcm_p = __clk_get_name(sclk_pcm_in);
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clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
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"div_pcm0", CLK_SET_RATE_PARENT,
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sclk_pcm_p, CLK_SET_RATE_PARENT,
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reg_base + ASS_CLK_GATE, 5, 0, &lock);
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for (i = 0; i < clk_data.clk_num; i++) {
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