[MIPS] Fix use of smp_processor_id() in preemptible code.
Freeing prom memory: 956kb freed Freeing firmware memory: 978944k freed Freeing unused kernel memory: 180k freed BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1 caller is r4k_dma_cache_wback_inv+0x144/0x2a0 Call Trace: [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0 ... CONFIG_DEBUG_PREEMPT is enabled. -- Bug cause is blast_dcache_range() in preemptible code [in r4k_dma_cache_wback_inv()]. blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that uses cpu_dcache_line_size(). It uses current_cpu_data that use smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT smp_processor_id emits BUG if we are executing with preemption enabled. Cpu options of cpu0 are assumed to be the superset of all processors. Can I make the same assumptions for cache line size and fix this issue the following way: Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
e1cca7e8d4
commit
54fd6441e0
|
@ -207,13 +207,13 @@
|
|||
#endif
|
||||
|
||||
#ifndef cpu_dcache_line_size
|
||||
#define cpu_dcache_line_size() current_cpu_data.dcache.linesz
|
||||
#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
|
||||
#endif
|
||||
#ifndef cpu_icache_line_size
|
||||
#define cpu_icache_line_size() current_cpu_data.icache.linesz
|
||||
#define cpu_icache_line_size() cpu_data[0].icache.linesz
|
||||
#endif
|
||||
#ifndef cpu_scache_line_size
|
||||
#define cpu_scache_line_size() current_cpu_data.scache.linesz
|
||||
#define cpu_scache_line_size() cpu_data[0].scache.linesz
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_FEATURES_H */
|
||||
|
|
Loading…
Reference in a new issue