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MLK-19113-1 ARM64: imx: enable l1.1 aspm for imx8mm 

In the L1.1 ASPM implementation, the CLK_REQ# should be
configured as open drain, pull up and input mode.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
pull/10/head
Richard Zhu 2018-08-02 13:31:20 +08:00 committed by Jason Liu
parent 0d6918d52d
commit 5556dd060b
2 changed files with 2 additions and 3 deletions
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3
arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts
View File

@ -232,7 +232,7 @@
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x41
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 /* open drain, pull up */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
@ -892,7 +892,6 @@
&pcie0{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
clkreq-gpio = <&gpio5 20 GPIO_ACTIVE_LOW>;
disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
ext_osc = <0>;

2
include/dt-bindings/pinctrl/pins-imx8mm.h
View File

@ -580,7 +580,7 @@
#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x12 0x0
#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0