KVM: PPC: Book3S HV: Implement architecture compatibility modes for POWER8
This allows us to select architecture 2.05 (POWER6) or 2.06 (POWER7) compatibility modes on a POWER8 processor. (Note that transactional memory is disabled for usermode if either or both of the PCR_TM_DIS and PCR_ARCH_206 bits are set.) Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -329,6 +329,8 @@
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#define SPRN_PCR 0x152 /* Processor compatibility register */
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#define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */
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#define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */
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#define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */
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#define PCR_ARCH_206 0x4 /* Architecture 2.06 */
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#define PCR_ARCH_205 0x2 /* Architecture 2.05 */
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#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
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#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
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@ -184,14 +184,28 @@ int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
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switch (arch_compat) {
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case PVR_ARCH_205:
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pcr = PCR_ARCH_205;
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/*
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* If an arch bit is set in PCR, all the defined
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* higher-order arch bits also have to be set.
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*/
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pcr = PCR_ARCH_206 | PCR_ARCH_205;
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break;
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case PVR_ARCH_206:
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case PVR_ARCH_206p:
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pcr = PCR_ARCH_206;
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break;
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case PVR_ARCH_207:
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break;
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default:
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return -EINVAL;
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}
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if (!cpu_has_feature(CPU_FTR_ARCH_207S)) {
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/* POWER7 can't emulate POWER8 */
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if (!(pcr & PCR_ARCH_206))
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return -EINVAL;
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pcr &= ~PCR_ARCH_206;
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}
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}
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spin_lock(&vc->lock);
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