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clk: hisilicon: fix lock assignment 

In clock driver initialize phase the spinlock is missed to assignment
to struct clkgate_separated, finally there have no locking to protect
exclusive accessing for clock registers.

This bug introduces the console has no output after enable coresight
driver on 96boards Hikey; this is because console using UART3, which
has shared the same register with coresight clock enabling bit. After
applied this patch it can assign lock properly to protect exclusive
accessing, and console can work well after enabled coresight modules.

Fixes: 0aa0c95f74 ("clk: hisilicon: add common clock support")
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
zero-colors
Leo Yan 2017-01-21 10:26:31 +08:00 committed by Stephen Boyd
parent de9b5a2404
commit 55da97e38c
1 changed files with 1 additions and 0 deletions
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drivers/clk/hisilicon/clkgate-separated.c
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@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
sclk->bit_idx = bit_idx;
sclk->flags = clk_gate_flags;
sclk->hw.init = &init;
sclk->lock = lock;
clk = clk_register(dev, &sclk->hw);
if (IS_ERR(clk))