[TG3]: Use constant for PHY register 0x1e.
Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -6594,8 +6594,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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u32 tmp;
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/* Clear CRC stats. */
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if (!tg3_readphy(tp, 0x1e, &tmp)) {
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tg3_writephy(tp, 0x1e, tmp | 0x8000);
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if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
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tg3_writephy(tp, MII_TG3_TEST1,
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tmp | MII_TG3_TEST1_CRC_EN);
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tg3_readphy(tp, 0x14, &tmp);
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}
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}
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@ -7419,8 +7420,9 @@ static unsigned long calc_crc_errors(struct tg3 *tp)
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u32 val;
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spin_lock_bh(&tp->lock);
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if (!tg3_readphy(tp, 0x1e, &val)) {
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tg3_writephy(tp, 0x1e, val | 0x8000);
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if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
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tg3_writephy(tp, MII_TG3_TEST1,
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val | MII_TG3_TEST1_CRC_EN);
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tg3_readphy(tp, 0x14, &val);
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} else
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val = 0;
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@ -1660,6 +1660,7 @@
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#define MII_TG3_TEST1 0x1e
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#define MII_TG3_TEST1_TRIM_EN 0x0010
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#define MII_TG3_TEST1_CRC_EN 0x8000
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/* There are two ways to manage the TX descriptors on the tigon3.
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* Either the descriptors are in host DMA'able memory, or they
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