ARM: shmobile: sh73a0 dtsi: Add missing INTCA0 clock for irqpin module
This clock drives the irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -94,6 +94,7 @@
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0 6 IRQ_TYPE_LEVEL_HIGH
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0 6 IRQ_TYPE_LEVEL_HIGH
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0 7 IRQ_TYPE_LEVEL_HIGH
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0 7 IRQ_TYPE_LEVEL_HIGH
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0 8 IRQ_TYPE_LEVEL_HIGH>;
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0 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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control-parent;
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control-parent;
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};
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};
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@ -114,6 +115,7 @@
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0 14 IRQ_TYPE_LEVEL_HIGH
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0 14 IRQ_TYPE_LEVEL_HIGH
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0 15 IRQ_TYPE_LEVEL_HIGH
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0 15 IRQ_TYPE_LEVEL_HIGH
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0 16 IRQ_TYPE_LEVEL_HIGH>;
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0 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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control-parent;
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control-parent;
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};
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};
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@ -134,6 +136,7 @@
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0 22 IRQ_TYPE_LEVEL_HIGH
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0 22 IRQ_TYPE_LEVEL_HIGH
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0 23 IRQ_TYPE_LEVEL_HIGH
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0 23 IRQ_TYPE_LEVEL_HIGH
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0 24 IRQ_TYPE_LEVEL_HIGH>;
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0 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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control-parent;
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control-parent;
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};
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};
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@ -154,6 +157,7 @@
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0 30 IRQ_TYPE_LEVEL_HIGH
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0 30 IRQ_TYPE_LEVEL_HIGH
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0 31 IRQ_TYPE_LEVEL_HIGH
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0 31 IRQ_TYPE_LEVEL_HIGH
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0 32 IRQ_TYPE_LEVEL_HIGH>;
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0 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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control-parent;
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control-parent;
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};
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};
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@ -698,5 +702,16 @@
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clock-output-names =
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clock-output-names =
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"iic3", "iic4", "keysc";
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"iic3", "iic4", "keysc";
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};
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};
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mstp5_clks: mstp5_clks@e6150144 {
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compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150144 4>, <0xe615003c 4>;
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clocks = <&cpg_clocks SH73A0_CLK_HP>;
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#clock-cells = <1>;
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clock-indices = <
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SH73A0_CLK_INTCA0
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>;
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clock-output-names =
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"intca0";
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};
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};
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};
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};
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};
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@ -76,4 +76,7 @@
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#define SH73A0_CLK_IIC4 10
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#define SH73A0_CLK_IIC4 10
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#define SH73A0_CLK_KEYSC 3
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#define SH73A0_CLK_KEYSC 3
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/* MSTP5 */
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#define SH73A0_CLK_INTCA0 8
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#endif
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#endif
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