bgmac: initialize the DMA controller of core rev >= 4
The DMA controller used in the device supported by GMAC with core rev >= 4 has some new options which are now set to the default values used in the Broadcom SDK. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -96,6 +96,19 @@ static void bgmac_dma_tx_enable(struct bgmac *bgmac,
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u32 ctl;
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ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
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if (bgmac->core->id.rev >= 4) {
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ctl &= ~BGMAC_DMA_TX_BL_MASK;
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ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
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ctl &= ~BGMAC_DMA_TX_MR_MASK;
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ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
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ctl &= ~BGMAC_DMA_TX_PC_MASK;
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ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
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ctl &= ~BGMAC_DMA_TX_PT_MASK;
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ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
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}
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ctl |= BGMAC_DMA_TX_ENABLE;
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ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
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bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
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@ -240,6 +253,16 @@ static void bgmac_dma_rx_enable(struct bgmac *bgmac,
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u32 ctl;
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ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
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if (bgmac->core->id.rev >= 4) {
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ctl &= ~BGMAC_DMA_RX_BL_MASK;
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ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
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ctl &= ~BGMAC_DMA_RX_PC_MASK;
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ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
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ctl &= ~BGMAC_DMA_RX_PT_MASK;
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ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
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}
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ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
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ctl |= BGMAC_DMA_RX_ENABLE;
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ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
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@ -237,9 +237,34 @@
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#define BGMAC_DMA_TX_SUSPEND 0x00000002
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#define BGMAC_DMA_TX_LOOPBACK 0x00000004
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#define BGMAC_DMA_TX_FLUSH 0x00000010
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#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
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#define BGMAC_DMA_TX_MR_SHIFT 6
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#define BGMAC_DMA_TX_MR_1 0
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#define BGMAC_DMA_TX_MR_2 1
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#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
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#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
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#define BGMAC_DMA_TX_ADDREXT_SHIFT 16
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#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
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#define BGMAC_DMA_TX_BL_SHIFT 18
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#define BGMAC_DMA_TX_BL_16 0
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#define BGMAC_DMA_TX_BL_32 1
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#define BGMAC_DMA_TX_BL_64 2
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#define BGMAC_DMA_TX_BL_128 3
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#define BGMAC_DMA_TX_BL_256 4
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#define BGMAC_DMA_TX_BL_512 5
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#define BGMAC_DMA_TX_BL_1024 6
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#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
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#define BGMAC_DMA_TX_PC_SHIFT 21
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#define BGMAC_DMA_TX_PC_0 0
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#define BGMAC_DMA_TX_PC_4 1
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#define BGMAC_DMA_TX_PC_8 2
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#define BGMAC_DMA_TX_PC_16 3
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#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
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#define BGMAC_DMA_TX_PT_SHIFT 24
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#define BGMAC_DMA_TX_PT_1 0
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#define BGMAC_DMA_TX_PT_2 1
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#define BGMAC_DMA_TX_PT_4 2
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#define BGMAC_DMA_TX_PT_8 3
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#define BGMAC_DMA_TX_INDEX 0x04
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#define BGMAC_DMA_TX_RINGLO 0x08
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#define BGMAC_DMA_TX_RINGHI 0x0C
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@ -267,8 +292,33 @@
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#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
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#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
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#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
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#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
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#define BGMAC_DMA_RX_MR_SHIFT 6
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#define BGMAC_DMA_TX_MR_1 0
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#define BGMAC_DMA_TX_MR_2 1
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#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
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#define BGMAC_DMA_RX_ADDREXT_SHIFT 16
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#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
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#define BGMAC_DMA_RX_BL_SHIFT 18
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#define BGMAC_DMA_RX_BL_16 0
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#define BGMAC_DMA_RX_BL_32 1
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#define BGMAC_DMA_RX_BL_64 2
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#define BGMAC_DMA_RX_BL_128 3
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#define BGMAC_DMA_RX_BL_256 4
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#define BGMAC_DMA_RX_BL_512 5
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#define BGMAC_DMA_RX_BL_1024 6
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#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
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#define BGMAC_DMA_RX_PC_SHIFT 21
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#define BGMAC_DMA_RX_PC_0 0
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#define BGMAC_DMA_RX_PC_4 1
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#define BGMAC_DMA_RX_PC_8 2
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#define BGMAC_DMA_RX_PC_16 3
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#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
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#define BGMAC_DMA_RX_PT_SHIFT 24
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#define BGMAC_DMA_RX_PT_1 0
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#define BGMAC_DMA_RX_PT_2 1
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#define BGMAC_DMA_RX_PT_4 2
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#define BGMAC_DMA_RX_PT_8 3
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#define BGMAC_DMA_RX_INDEX 0x24
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#define BGMAC_DMA_RX_RINGLO 0x28
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#define BGMAC_DMA_RX_RINGHI 0x2C
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