pinctrl: sunxi: add driver for V3s SoC
V3s SoC features only a pin controller (for the lack of CPUs part). Add a driver for this controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>zero-colors
Icenowy Zheng
Linus Walleij
parent
3775dac1bc
commit
56d9e4a760
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@ -55,6 +55,10 @@ config PINCTRL_SUN8I_H3_R
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI_COMMON
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config PINCTRL_SUN8I_V3S
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN9I_A80
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def_bool MACH_SUN9I
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select PINCTRL_SUNXI
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@ -15,5 +15,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
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obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
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obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
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obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
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obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
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obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
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obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
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@ -0,0 +1,321 @@
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/*
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* Allwinner V3s SoCs pinctrl driver.
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*
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* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
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*
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* Based on pinctrl-sun8i-h3.c, which is:
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* Based on pinctrl-sun8i-a23.c, which is:
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* Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
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* Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun8i_v3s_pins[] = {
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* D1 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "pwm0"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "pwm1"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
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SUNXI_FUNCTION(0x3, "uart0"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
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SUNXI_FUNCTION(0x3, "uart0"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc2"), /* CLK */
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SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc2"), /* CMD */
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SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc2"), /* RST */
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SUNXI_FUNCTION(0x3, "spi0")), /* CS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */
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SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
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SUNXI_FUNCTION(0x3, "lcd")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
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SUNXI_FUNCTION(0x3, "lcd")), /* DE */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
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SUNXI_FUNCTION(0x3, "lcd")), /* HSYNC */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
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SUNXI_FUNCTION(0x3, "lcd")), /* VSYNC */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D0 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D1 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D2 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D3 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D4 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D5 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D7 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D6 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D10 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D7 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D11 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D8 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D12 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D9 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D13 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D10 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D14 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D11 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D15 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D12 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D18 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D13 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D19 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D14 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D20 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* D15 */
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SUNXI_FUNCTION(0x3, "lcd")), /* D21 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* FIELD */
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SUNXI_FUNCTION(0x3, "csi_mipi")), /* MCLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* SCK */
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SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
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SUNXI_FUNCTION(0x4, "uart1")), /* TX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "csi"), /* SDA */
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SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
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SUNXI_FUNCTION(0x4, "uart1")), /* RX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 23),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "lcd"), /* D22 */
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SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 24),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x3, "lcd"), /* D23 */
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SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
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SUNXI_FUNCTION(0x3, "jtag")), /* MS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
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SUNXI_FUNCTION(0x3, "jtag")), /* DI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
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SUNXI_FUNCTION(0x3, "uart0")), /* TX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
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SUNXI_FUNCTION(0x3, "jtag")), /* DO */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
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SUNXI_FUNCTION(0x3, "uart0")), /* RX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
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SUNXI_FUNCTION(0x3, "jtag")), /* CK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out")),
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
|
||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
|
||||
};
|
||||
|
||||
static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
|
||||
.pins = sun8i_v3s_pins,
|
||||
.npins = ARRAY_SIZE(sun8i_v3s_pins),
|
||||
.irq_banks = 2,
|
||||
.irq_read_needs_mux = true
|
||||
};
|
||||
|
||||
static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
return sunxi_pinctrl_init(pdev,
|
||||
&sun8i_v3s_pinctrl_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id sun8i_v3s_pinctrl_match[] = {
|
||||
{ .compatible = "allwinner,sun8i-v3s-pinctrl", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver sun8i_v3s_pinctrl_driver = {
|
||||
.probe = sun8i_v3s_pinctrl_probe,
|
||||
.driver = {
|
||||
.name = "sun8i-v3s-pinctrl",
|
||||
.of_match_table = sun8i_v3s_pinctrl_match,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(sun8i_v3s_pinctrl_driver);
|
||||
Loading…
Reference in New Issue