ASoC: fsl_ssi: Go back to explicit register defaults
Commit 5c408fee25
("ASoC: fsl_ssi: remove explicit register defaults")
causes the driver to fail to probe:
fsl-ssi-dai 2028000.ssi: No cache defaults, reading back from HW
fsl-ssi-dai 2028000.ssi: Failed to init register map
fsl-ssi-dai: probe of 2028000.ssi failed with error -22
, so revert this commit.
Reported-by: Mika Penttilä <mika.penttila@nextfour.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
parent
81f70ba233
commit
56e5fd8feb
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@ -112,6 +112,20 @@ struct fsl_ssi_rxtx_reg_val {
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struct fsl_ssi_reg_val tx;
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};
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static const struct reg_default fsl_ssi_reg_defaults[] = {
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{CCSR_SSI_SCR, 0x00000000},
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{CCSR_SSI_SIER, 0x00003003},
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{CCSR_SSI_STCR, 0x00000200},
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{CCSR_SSI_SRCR, 0x00000200},
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{CCSR_SSI_STCCR, 0x00040000},
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{CCSR_SSI_SRCCR, 0x00040000},
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{CCSR_SSI_SACNT, 0x00000000},
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{CCSR_SSI_STMSK, 0x00000000},
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{CCSR_SSI_SRMSK, 0x00000000},
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{CCSR_SSI_SACCEN, 0x00000000},
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{CCSR_SSI_SACCDIS, 0x00000000},
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};
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static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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@ -176,7 +190,8 @@ static const struct regmap_config fsl_ssi_regconfig = {
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.val_bits = 32,
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.reg_stride = 4,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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.num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1,
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.reg_defaults = fsl_ssi_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults),
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.readable_reg = fsl_ssi_readable_reg,
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.volatile_reg = fsl_ssi_volatile_reg,
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.precious_reg = fsl_ssi_precious_reg,
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@ -186,7 +201,6 @@ static const struct regmap_config fsl_ssi_regconfig = {
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struct fsl_ssi_soc_data {
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bool imx;
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bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
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bool offline_config;
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u32 sisr_write_mask;
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};
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@ -289,7 +303,6 @@ static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
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static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
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.imx = true,
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.imx21regs = true,
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.offline_config = true,
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.sisr_write_mask = 0,
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};
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@ -573,12 +586,8 @@ static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
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*/
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regmap_write(regs, CCSR_SSI_SACNT,
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CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
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/* no SACC{ST,EN,DIS} regs on imx21-class SSI */
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if (!ssi_private->soc->imx21regs) {
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regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
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regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
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}
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regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
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regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
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/*
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* Enable SSI, Transmit and Receive. AC97 has to communicate with the
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@ -1388,7 +1397,6 @@ static int fsl_ssi_probe(struct platform_device *pdev)
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struct resource *res;
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void __iomem *iomem;
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char name[64];
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struct regmap_config regconfig = fsl_ssi_regconfig;
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of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
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if (!of_id || !of_id->data)
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@ -1436,25 +1444,15 @@ static int fsl_ssi_probe(struct platform_device *pdev)
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return PTR_ERR(iomem);
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ssi_private->ssi_phys = res->start;
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if (ssi_private->soc->imx21regs) {
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/*
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* According to datasheet imx21-class SSI
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* don't have SACC{ST,EN,DIS} regs.
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*/
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regconfig.max_register = CCSR_SSI_SRMSK;
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regconfig.num_reg_defaults_raw =
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CCSR_SSI_SRMSK / sizeof(uint32_t) + 1;
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}
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ret = of_property_match_string(np, "clock-names", "ipg");
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if (ret < 0) {
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ssi_private->has_ipg_clk_name = false;
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ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
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®config);
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&fsl_ssi_regconfig);
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} else {
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ssi_private->has_ipg_clk_name = true;
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ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
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"ipg", iomem, ®config);
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"ipg", iomem, &fsl_ssi_regconfig);
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}
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if (IS_ERR(ssi_private->regs)) {
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dev_err(&pdev->dev, "Failed to init register map\n");
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