i2c: Blackfin TWI: fix REPEAT START mode doesn't repeat
Avoid rewrite TWI MASTER_CTL reg when issue next message In i2c repeat transfer mode, byte count of next message should be filled into part of the TWI MASTER_CTL reg when interrupt MCOMP of last message transfer is triggered. But, other bits in this reg should not be touched. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Bryan Wu <cooloney@kernel.org> [ben-linux@fluff.org: shorted subject] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -196,8 +196,6 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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/* remove restart bit and enable master receive */
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) & ~RSTART);
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) | MEN | MDIR);
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SSYNC();
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} else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
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iface->cur_msg+1 < iface->msg_num) {
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@ -222,18 +220,19 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
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}
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if (iface->pmsg[iface->cur_msg].len <= 255)
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write_MASTER_CTL(iface,
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iface->pmsg[iface->cur_msg].len << 6);
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) &
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(~(0xff << 6))) |
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(iface->pmsg[iface->cur_msg].len << 6));
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else {
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write_MASTER_CTL(iface, 0xff << 6);
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write_MASTER_CTL(iface,
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(read_MASTER_CTL(iface) |
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(0xff << 6)));
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iface->manual_stop = 1;
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}
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/* remove restart bit and enable master receive */
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write_MASTER_CTL(iface,
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read_MASTER_CTL(iface) & ~RSTART);
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write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
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MEN | ((iface->read_write == I2C_SMBUS_READ) ?
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MDIR : 0));
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SSYNC();
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} else {
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iface->result = 1;
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