[media] st-hva: multi-format video encoder V4L2 driver
This patch adds V4L2 HVA (Hardware Video Accelerator) video encoder driver for STMicroelectronics SoC. It uses the V4L2 mem2mem framework. This patch only contains the core parts of the driver: - the V4L2 interface with the userland (hva-v4l2.c) - the hardware services (hva-hw.c) - the memory management utilities (hva-mem.c) This patch doesn't include the support of specific codec (e.g. H.264) video encoding: this support is part of subsequent patches. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Signed-off-by: Jean-Christophe Trotin <jean-christophe.trotin@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>steinar/wifi_calib_4_9_kernel
Jean-Christophe Trotin
Mauro Carvalho Chehab
parent
9ef0b3f3f8
commit
57b2c0628b
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@ -257,6 +257,21 @@ config VIDEO_STI_BDISP
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help
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This v4l2 mem2mem driver is a 2D blitter for STMicroelectronics SoC.
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config VIDEO_STI_HVA
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tristate "STMicroelectronics HVA multi-format video encoder V4L2 driver"
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depends on VIDEO_DEV && VIDEO_V4L2
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depends on HAS_DMA
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depends on ARCH_STI || COMPILE_TEST
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select VIDEOBUF2_DMA_CONTIG
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select V4L2_MEM2MEM_DEV
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help
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This V4L2 driver enables HVA (Hardware Video Accelerator) multi-format
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video encoder of STMicroelectronics SoC, allowing hardware encoding of
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raw uncompressed formats in various compressed video bitstreams format.
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To compile this driver as a module, choose M here:
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the module will be called st-hva.
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config VIDEO_SH_VEU
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tristate "SuperH VEU mem2mem video processing driver"
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depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
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@ -35,6 +35,7 @@ obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D) += s5p-g2d/
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obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC) += exynos-gsc/
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obj-$(CONFIG_VIDEO_STI_BDISP) += sti/bdisp/
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obj-$(CONFIG_VIDEO_STI_HVA) += sti/hva/
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obj-$(CONFIG_DVB_C8SECTPFE) += sti/c8sectpfe/
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obj-$(CONFIG_BLACKFIN) += blackfin/
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@ -0,0 +1,2 @@
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obj-$(CONFIG_VIDEO_STI_HVA) := st-hva.o
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st-hva-y := hva-v4l2.o hva-hw.o hva-mem.o
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@ -0,0 +1,538 @@
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/*
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* Copyright (C) STMicroelectronics SA 2015
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* Authors: Yannick Fertre <yannick.fertre@st.com>
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* Hugues Fruchet <hugues.fruchet@st.com>
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "hva.h"
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#include "hva-hw.h"
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/* HVA register offsets */
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#define HVA_HIF_REG_RST 0x0100U
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#define HVA_HIF_REG_RST_ACK 0x0104U
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#define HVA_HIF_REG_MIF_CFG 0x0108U
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#define HVA_HIF_REG_HEC_MIF_CFG 0x010CU
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#define HVA_HIF_REG_CFL 0x0110U
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#define HVA_HIF_FIFO_CMD 0x0114U
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#define HVA_HIF_FIFO_STS 0x0118U
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#define HVA_HIF_REG_SFL 0x011CU
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#define HVA_HIF_REG_IT_ACK 0x0120U
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#define HVA_HIF_REG_ERR_IT_ACK 0x0124U
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#define HVA_HIF_REG_LMI_ERR 0x0128U
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#define HVA_HIF_REG_EMI_ERR 0x012CU
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#define HVA_HIF_REG_HEC_MIF_ERR 0x0130U
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#define HVA_HIF_REG_HEC_STS 0x0134U
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#define HVA_HIF_REG_HVC_STS 0x0138U
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#define HVA_HIF_REG_HJE_STS 0x013CU
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#define HVA_HIF_REG_CNT 0x0140U
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#define HVA_HIF_REG_HEC_CHKSYN_DIS 0x0144U
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#define HVA_HIF_REG_CLK_GATING 0x0148U
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#define HVA_HIF_REG_VERSION 0x014CU
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#define HVA_HIF_REG_BSM 0x0150U
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/* define value for version id register (HVA_HIF_REG_VERSION) */
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#define VERSION_ID_MASK 0x0000FFFF
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/* define values for BSM register (HVA_HIF_REG_BSM) */
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#define BSM_CFG_VAL1 0x0003F000
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#define BSM_CFG_VAL2 0x003F0000
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/* define values for memory interface register (HVA_HIF_REG_MIF_CFG) */
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#define MIF_CFG_VAL1 0x04460446
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#define MIF_CFG_VAL2 0x04460806
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#define MIF_CFG_VAL3 0x00000000
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/* define value for HEC memory interface register (HVA_HIF_REG_MIF_CFG) */
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#define HEC_MIF_CFG_VAL 0x000000C4
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/* Bits definition for clock gating register (HVA_HIF_REG_CLK_GATING) */
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#define CLK_GATING_HVC BIT(0)
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#define CLK_GATING_HEC BIT(1)
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#define CLK_GATING_HJE BIT(2)
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/* fix hva clock rate */
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#define CLK_RATE 300000000
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/* fix delay for pmruntime */
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#define AUTOSUSPEND_DELAY_MS 3
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/*
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* hw encode error values
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* NO_ERROR: Success, Task OK
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* H264_BITSTREAM_OVERSIZE: VECH264 Bitstream size > bitstream buffer
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* H264_FRAME_SKIPPED: VECH264 Frame skipped (refers to CPB Buffer Size)
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* H264_SLICE_LIMIT_SIZE: VECH264 MB > slice limit size
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* H264_MAX_SLICE_NUMBER: VECH264 max slice number reached
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* H264_SLICE_READY: VECH264 Slice ready
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* TASK_LIST_FULL: HVA/FPC task list full
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(discard latest transform command)
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* UNKNOWN_COMMAND: Transform command not known by HVA/FPC
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* WRONG_CODEC_OR_RESOLUTION: Wrong Codec or Resolution Selection
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* NO_INT_COMPLETION: Time-out on interrupt completion
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* LMI_ERR: Local Memory Interface Error
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* EMI_ERR: External Memory Interface Error
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* HECMI_ERR: HEC Memory Interface Error
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*/
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enum hva_hw_error {
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NO_ERROR = 0x0,
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H264_BITSTREAM_OVERSIZE = 0x2,
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H264_FRAME_SKIPPED = 0x4,
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H264_SLICE_LIMIT_SIZE = 0x5,
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H264_MAX_SLICE_NUMBER = 0x7,
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H264_SLICE_READY = 0x8,
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TASK_LIST_FULL = 0xF0,
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UNKNOWN_COMMAND = 0xF1,
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WRONG_CODEC_OR_RESOLUTION = 0xF4,
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NO_INT_COMPLETION = 0x100,
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LMI_ERR = 0x101,
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EMI_ERR = 0x102,
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HECMI_ERR = 0x103,
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};
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static irqreturn_t hva_hw_its_interrupt(int irq, void *data)
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{
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struct hva_dev *hva = data;
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/* read status registers */
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hva->sts_reg = readl_relaxed(hva->regs + HVA_HIF_FIFO_STS);
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hva->sfl_reg = readl_relaxed(hva->regs + HVA_HIF_REG_SFL);
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/* acknowledge interruption */
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writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
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return IRQ_WAKE_THREAD;
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}
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static irqreturn_t hva_hw_its_irq_thread(int irq, void *arg)
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{
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struct hva_dev *hva = arg;
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struct device *dev = hva_to_dev(hva);
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u32 status = hva->sts_reg & 0xFF;
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u8 ctx_id = 0;
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struct hva_ctx *ctx = NULL;
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dev_dbg(dev, "%s %s: status: 0x%02x fifo level: 0x%02x\n",
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HVA_PREFIX, __func__, hva->sts_reg & 0xFF, hva->sfl_reg & 0xF);
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/*
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* status: task_id[31:16] client_id[15:8] status[7:0]
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* the context identifier is retrieved from the client identifier
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*/
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ctx_id = (hva->sts_reg & 0xFF00) >> 8;
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if (ctx_id >= HVA_MAX_INSTANCES) {
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dev_err(dev, "%s %s: bad context identifier: %d\n",
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ctx->name, __func__, ctx_id);
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ctx->hw_err = true;
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goto out;
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}
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ctx = hva->instances[ctx_id];
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if (!ctx)
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goto out;
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switch (status) {
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case NO_ERROR:
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dev_dbg(dev, "%s %s: no error\n",
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ctx->name, __func__);
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ctx->hw_err = false;
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break;
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case H264_SLICE_READY:
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dev_dbg(dev, "%s %s: h264 slice ready\n",
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ctx->name, __func__);
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ctx->hw_err = false;
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break;
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case H264_FRAME_SKIPPED:
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dev_dbg(dev, "%s %s: h264 frame skipped\n",
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ctx->name, __func__);
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ctx->hw_err = false;
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break;
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case H264_BITSTREAM_OVERSIZE:
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dev_err(dev, "%s %s:h264 bitstream oversize\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case H264_SLICE_LIMIT_SIZE:
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dev_err(dev, "%s %s: h264 slice limit size is reached\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case H264_MAX_SLICE_NUMBER:
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dev_err(dev, "%s %s: h264 max slice number is reached\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case TASK_LIST_FULL:
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dev_err(dev, "%s %s:task list full\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case UNKNOWN_COMMAND:
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dev_err(dev, "%s %s: command not known\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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case WRONG_CODEC_OR_RESOLUTION:
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dev_err(dev, "%s %s: wrong codec or resolution\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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default:
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dev_err(dev, "%s %s: status not recognized\n",
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ctx->name, __func__);
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ctx->hw_err = true;
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break;
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}
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out:
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complete(&hva->interrupt);
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return IRQ_HANDLED;
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}
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static irqreturn_t hva_hw_err_interrupt(int irq, void *data)
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{
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struct hva_dev *hva = data;
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/* read status registers */
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hva->sts_reg = readl_relaxed(hva->regs + HVA_HIF_FIFO_STS);
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hva->sfl_reg = readl_relaxed(hva->regs + HVA_HIF_REG_SFL);
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/* read error registers */
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hva->lmi_err_reg = readl_relaxed(hva->regs + HVA_HIF_REG_LMI_ERR);
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hva->emi_err_reg = readl_relaxed(hva->regs + HVA_HIF_REG_EMI_ERR);
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hva->hec_mif_err_reg = readl_relaxed(hva->regs +
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HVA_HIF_REG_HEC_MIF_ERR);
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/* acknowledge interruption */
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writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
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return IRQ_WAKE_THREAD;
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}
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static irqreturn_t hva_hw_err_irq_thread(int irq, void *arg)
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{
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struct hva_dev *hva = arg;
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struct device *dev = hva_to_dev(hva);
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u8 ctx_id = 0;
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struct hva_ctx *ctx;
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dev_dbg(dev, "%s status: 0x%02x fifo level: 0x%02x\n",
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HVA_PREFIX, hva->sts_reg & 0xFF, hva->sfl_reg & 0xF);
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/*
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* status: task_id[31:16] client_id[15:8] status[7:0]
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* the context identifier is retrieved from the client identifier
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*/
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ctx_id = (hva->sts_reg & 0xFF00) >> 8;
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if (ctx_id >= HVA_MAX_INSTANCES) {
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dev_err(dev, "%s bad context identifier: %d\n", HVA_PREFIX,
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ctx_id);
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goto out;
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}
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ctx = hva->instances[ctx_id];
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if (!ctx)
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goto out;
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if (hva->lmi_err_reg) {
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dev_err(dev, "%s local memory interface error: 0x%08x\n",
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ctx->name, hva->lmi_err_reg);
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ctx->hw_err = true;
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}
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if (hva->lmi_err_reg) {
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dev_err(dev, "%s external memory interface error: 0x%08x\n",
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ctx->name, hva->emi_err_reg);
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ctx->hw_err = true;
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}
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if (hva->hec_mif_err_reg) {
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dev_err(dev, "%s hec memory interface error: 0x%08x\n",
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ctx->name, hva->hec_mif_err_reg);
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ctx->hw_err = true;
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}
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out:
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complete(&hva->interrupt);
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return IRQ_HANDLED;
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}
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static unsigned long int hva_hw_get_ip_version(struct hva_dev *hva)
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{
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struct device *dev = hva_to_dev(hva);
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unsigned long int version;
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if (pm_runtime_get_sync(dev) < 0) {
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dev_err(dev, "%s failed to get pm_runtime\n", HVA_PREFIX);
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mutex_unlock(&hva->protect_mutex);
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return -EFAULT;
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}
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version = readl_relaxed(hva->regs + HVA_HIF_REG_VERSION) &
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VERSION_ID_MASK;
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pm_runtime_put_autosuspend(dev);
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switch (version) {
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case HVA_VERSION_V400:
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dev_dbg(dev, "%s IP hardware version 0x%lx\n",
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HVA_PREFIX, version);
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break;
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default:
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dev_err(dev, "%s unknown IP hardware version 0x%lx\n",
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HVA_PREFIX, version);
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version = HVA_VERSION_UNKNOWN;
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break;
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}
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return version;
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}
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int hva_hw_probe(struct platform_device *pdev, struct hva_dev *hva)
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{
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struct device *dev = &pdev->dev;
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struct resource *regs;
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struct resource *esram;
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int ret;
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WARN_ON(!hva);
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/* get memory for registers */
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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hva->regs = devm_ioremap_resource(dev, regs);
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if (IS_ERR_OR_NULL(hva->regs)) {
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dev_err(dev, "%s failed to get regs\n", HVA_PREFIX);
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return PTR_ERR(hva->regs);
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}
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/* get memory for esram */
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esram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (IS_ERR_OR_NULL(esram)) {
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dev_err(dev, "%s failed to get esram\n", HVA_PREFIX);
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return PTR_ERR(esram);
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}
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hva->esram_addr = esram->start;
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hva->esram_size = resource_size(esram);
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dev_info(dev, "%s esram reserved for address: 0x%x size:%d\n",
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HVA_PREFIX, hva->esram_addr, hva->esram_size);
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/* get clock resource */
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hva->clk = devm_clk_get(dev, "clk_hva");
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if (IS_ERR(hva->clk)) {
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dev_err(dev, "%s failed to get clock\n", HVA_PREFIX);
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return PTR_ERR(hva->clk);
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}
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ret = clk_prepare(hva->clk);
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if (ret < 0) {
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dev_err(dev, "%s failed to prepare clock\n", HVA_PREFIX);
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hva->clk = ERR_PTR(-EINVAL);
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return ret;
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}
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/* get status interruption resource */
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ret = platform_get_irq(pdev, 0);
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if (ret < 0) {
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dev_err(dev, "%s failed to get status IRQ\n", HVA_PREFIX);
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goto err_clk;
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}
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hva->irq_its = ret;
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ret = devm_request_threaded_irq(dev, hva->irq_its, hva_hw_its_interrupt,
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hva_hw_its_irq_thread,
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IRQF_ONESHOT,
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"hva_its_irq", hva);
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if (ret) {
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dev_err(dev, "%s failed to install status IRQ 0x%x\n",
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HVA_PREFIX, hva->irq_its);
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goto err_clk;
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}
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disable_irq(hva->irq_its);
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/* get error interruption resource */
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ret = platform_get_irq(pdev, 1);
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if (ret < 0) {
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dev_err(dev, "%s failed to get error IRQ\n", HVA_PREFIX);
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goto err_clk;
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}
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hva->irq_err = ret;
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ret = devm_request_threaded_irq(dev, hva->irq_err, hva_hw_err_interrupt,
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hva_hw_err_irq_thread,
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IRQF_ONESHOT,
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"hva_err_irq", hva);
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if (ret) {
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dev_err(dev, "%s failed to install error IRQ 0x%x\n",
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HVA_PREFIX, hva->irq_err);
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goto err_clk;
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}
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disable_irq(hva->irq_err);
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/* initialise protection mutex */
|
||||
mutex_init(&hva->protect_mutex);
|
||||
|
||||
/* initialise completion signal */
|
||||
init_completion(&hva->interrupt);
|
||||
|
||||
/* initialise runtime power management */
|
||||
pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_DELAY_MS);
|
||||
pm_runtime_use_autosuspend(dev);
|
||||
pm_runtime_set_suspended(dev);
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "%s failed to set PM\n", HVA_PREFIX);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
/* check IP hardware version */
|
||||
hva->ip_version = hva_hw_get_ip_version(hva);
|
||||
|
||||
if (hva->ip_version == HVA_VERSION_UNKNOWN) {
|
||||
ret = -EINVAL;
|
||||
goto err_pm;
|
||||
}
|
||||
|
||||
dev_info(dev, "%s found hva device (version 0x%lx)\n", HVA_PREFIX,
|
||||
hva->ip_version);
|
||||
|
||||
return 0;
|
||||
|
||||
err_pm:
|
||||
pm_runtime_put(dev);
|
||||
err_clk:
|
||||
if (hva->clk)
|
||||
clk_unprepare(hva->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void hva_hw_remove(struct hva_dev *hva)
|
||||
{
|
||||
struct device *dev = hva_to_dev(hva);
|
||||
|
||||
disable_irq(hva->irq_its);
|
||||
disable_irq(hva->irq_err);
|
||||
|
||||
pm_runtime_put_autosuspend(dev);
|
||||
pm_runtime_disable(dev);
|
||||
}
|
||||
|
||||
int hva_hw_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct hva_dev *hva = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(hva->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hva_hw_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct hva_dev *hva = dev_get_drvdata(dev);
|
||||
|
||||
if (clk_prepare_enable(hva->clk)) {
|
||||
dev_err(hva->dev, "%s failed to prepare hva clk\n",
|
||||
HVA_PREFIX);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (clk_set_rate(hva->clk, CLK_RATE)) {
|
||||
dev_err(dev, "%s failed to set clock frequency\n",
|
||||
HVA_PREFIX);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int hva_hw_execute_task(struct hva_ctx *ctx, enum hva_hw_cmd_type cmd,
|
||||
struct hva_buffer *task)
|
||||
{
|
||||
struct hva_dev *hva = ctx_to_hdev(ctx);
|
||||
struct device *dev = hva_to_dev(hva);
|
||||
u8 client_id = ctx->id;
|
||||
int ret;
|
||||
u32 reg = 0;
|
||||
|
||||
mutex_lock(&hva->protect_mutex);
|
||||
|
||||
/* enable irqs */
|
||||
enable_irq(hva->irq_its);
|
||||
enable_irq(hva->irq_err);
|
||||
|
||||
if (pm_runtime_get_sync(dev) < 0) {
|
||||
dev_err(dev, "%s failed to get pm_runtime\n", ctx->name);
|
||||
ret = -EFAULT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
reg = readl_relaxed(hva->regs + HVA_HIF_REG_CLK_GATING);
|
||||
switch (cmd) {
|
||||
case H264_ENC:
|
||||
reg |= CLK_GATING_HVC;
|
||||
break;
|
||||
default:
|
||||
dev_dbg(dev, "%s unknown command 0x%x\n", ctx->name, cmd);
|
||||
ret = -EFAULT;
|
||||
goto out;
|
||||
}
|
||||
writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
|
||||
|
||||
dev_dbg(dev, "%s %s: write configuration registers\n", ctx->name,
|
||||
__func__);
|
||||
|
||||
/* byte swap config */
|
||||
writel_relaxed(BSM_CFG_VAL1, hva->regs + HVA_HIF_REG_BSM);
|
||||
|
||||
/* define Max Opcode Size and Max Message Size for LMI and EMI */
|
||||
writel_relaxed(MIF_CFG_VAL3, hva->regs + HVA_HIF_REG_MIF_CFG);
|
||||
writel_relaxed(HEC_MIF_CFG_VAL, hva->regs + HVA_HIF_REG_HEC_MIF_CFG);
|
||||
|
||||
/*
|
||||
* command FIFO: task_id[31:16] client_id[15:8] command_type[7:0]
|
||||
* the context identifier is provided as client identifier to the
|
||||
* hardware, and is retrieved in the interrupt functions from the
|
||||
* status register
|
||||
*/
|
||||
dev_dbg(dev, "%s %s: send task (cmd: %d, task_desc: %pad)\n",
|
||||
ctx->name, __func__, cmd + (client_id << 8), &task->paddr);
|
||||
writel_relaxed(cmd + (client_id << 8), hva->regs + HVA_HIF_FIFO_CMD);
|
||||
writel_relaxed(task->paddr, hva->regs + HVA_HIF_FIFO_CMD);
|
||||
|
||||
if (!wait_for_completion_timeout(&hva->interrupt,
|
||||
msecs_to_jiffies(2000))) {
|
||||
dev_err(dev, "%s %s: time out on completion\n", ctx->name,
|
||||
__func__);
|
||||
ret = -EFAULT;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* get encoding status */
|
||||
ret = ctx->hw_err ? -EFAULT : 0;
|
||||
|
||||
out:
|
||||
disable_irq(hva->irq_its);
|
||||
disable_irq(hva->irq_err);
|
||||
|
||||
switch (cmd) {
|
||||
case H264_ENC:
|
||||
reg &= ~CLK_GATING_HVC;
|
||||
writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
|
||||
break;
|
||||
default:
|
||||
dev_dbg(dev, "%s unknown command 0x%x\n", ctx->name, cmd);
|
||||
}
|
||||
|
||||
pm_runtime_put_autosuspend(dev);
|
||||
mutex_unlock(&hva->protect_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright (C) STMicroelectronics SA 2015
|
||||
* Authors: Yannick Fertre <yannick.fertre@st.com>
|
||||
* Hugues Fruchet <hugues.fruchet@st.com>
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*/
|
||||
|
||||
#ifndef HVA_HW_H
|
||||
#define HVA_HW_H
|
||||
|
||||
#include "hva-mem.h"
|
||||
|
||||
/* HVA Versions */
|
||||
#define HVA_VERSION_UNKNOWN 0x000
|
||||
#define HVA_VERSION_V400 0x400
|
||||
|
||||
/* HVA command types */
|
||||
enum hva_hw_cmd_type {
|
||||
/* RESERVED = 0x00 */
|
||||
/* RESERVED = 0x01 */
|
||||
H264_ENC = 0x02,
|
||||
/* RESERVED = 0x03 */
|
||||
/* RESERVED = 0x04 */
|
||||
/* RESERVED = 0x05 */
|
||||
/* RESERVED = 0x06 */
|
||||
/* RESERVED = 0x07 */
|
||||
REMOVE_CLIENT = 0x08,
|
||||
FREEZE_CLIENT = 0x09,
|
||||
START_CLIENT = 0x0A,
|
||||
FREEZE_ALL = 0x0B,
|
||||
START_ALL = 0x0C,
|
||||
REMOVE_ALL = 0x0D
|
||||
};
|
||||
|
||||
int hva_hw_probe(struct platform_device *pdev, struct hva_dev *hva);
|
||||
void hva_hw_remove(struct hva_dev *hva);
|
||||
int hva_hw_runtime_suspend(struct device *dev);
|
||||
int hva_hw_runtime_resume(struct device *dev);
|
||||
int hva_hw_execute_task(struct hva_ctx *ctx, enum hva_hw_cmd_type cmd,
|
||||
struct hva_buffer *task);
|
||||
|
||||
#endif /* HVA_HW_H */
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (C) STMicroelectronics SA 2015
|
||||
* Authors: Yannick Fertre <yannick.fertre@st.com>
|
||||
* Hugues Fruchet <hugues.fruchet@st.com>
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*/
|
||||
|
||||
#include "hva.h"
|
||||
#include "hva-mem.h"
|
||||
|
||||
int hva_mem_alloc(struct hva_ctx *ctx, u32 size, const char *name,
|
||||
struct hva_buffer **buf)
|
||||
{
|
||||
struct device *dev = ctx_to_dev(ctx);
|
||||
struct hva_buffer *b;
|
||||
dma_addr_t paddr;
|
||||
void *base;
|
||||
|
||||
b = devm_kzalloc(dev, sizeof(*b), GFP_KERNEL);
|
||||
if (!b)
|
||||
return -ENOMEM;
|
||||
|
||||
base = dma_alloc_attrs(dev, size, &paddr, GFP_KERNEL | GFP_DMA,
|
||||
DMA_ATTR_WRITE_COMBINE);
|
||||
if (!base) {
|
||||
dev_err(dev, "%s %s : dma_alloc_attrs failed for %s (size=%d)\n",
|
||||
ctx->name, __func__, name, size);
|
||||
devm_kfree(dev, b);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
b->size = size;
|
||||
b->paddr = paddr;
|
||||
b->vaddr = base;
|
||||
b->name = name;
|
||||
|
||||
dev_dbg(dev,
|
||||
"%s allocate %d bytes of HW memory @(virt=%p, phy=%pad): %s\n",
|
||||
ctx->name, size, b->vaddr, &b->paddr, b->name);
|
||||
|
||||
/* return hva buffer to user */
|
||||
*buf = b;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void hva_mem_free(struct hva_ctx *ctx, struct hva_buffer *buf)
|
||||
{
|
||||
struct device *dev = ctx_to_dev(ctx);
|
||||
|
||||
dev_dbg(dev,
|
||||
"%s free %d bytes of HW memory @(virt=%p, phy=%pad): %s\n",
|
||||
ctx->name, buf->size, buf->vaddr, &buf->paddr, buf->name);
|
||||
|
||||
dma_free_attrs(dev, buf->size, buf->vaddr, buf->paddr,
|
||||
DMA_ATTR_WRITE_COMBINE);
|
||||
|
||||
devm_kfree(dev, buf);
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (C) STMicroelectronics SA 2015
|
||||
* Authors: Yannick Fertre <yannick.fertre@st.com>
|
||||
* Hugues Fruchet <hugues.fruchet@st.com>
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*/
|
||||
|
||||
#ifndef HVA_MEM_H
|
||||
#define HVA_MEM_H
|
||||
|
||||
/**
|
||||
* struct hva_buffer - hva buffer
|
||||
*
|
||||
* @name: name of requester
|
||||
* @paddr: physical address (for hardware)
|
||||
* @vaddr: virtual address (kernel can read/write)
|
||||
* @size: size of buffer
|
||||
*/
|
||||
struct hva_buffer {
|
||||
const char *name;
|
||||
dma_addr_t paddr;
|
||||
void *vaddr;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
int hva_mem_alloc(struct hva_ctx *ctx,
|
||||
__u32 size,
|
||||
const char *name,
|
||||
struct hva_buffer **buf);
|
||||
|
||||
void hva_mem_free(struct hva_ctx *ctx,
|
||||
struct hva_buffer *buf);
|
||||
|
||||
#endif /* HVA_MEM_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,290 @@
|
|||
/*
|
||||
* Copyright (C) STMicroelectronics SA 2015
|
||||
* Authors: Yannick Fertre <yannick.fertre@st.com>
|
||||
* Hugues Fruchet <hugues.fruchet@st.com>
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*/
|
||||
|
||||
#ifndef HVA_H
|
||||
#define HVA_H
|
||||
|
||||
#include <media/v4l2-ctrls.h>
|
||||
#include <media/v4l2-device.h>
|
||||
#include <media/videobuf2-v4l2.h>
|
||||
#include <media/v4l2-mem2mem.h>
|
||||
|
||||
#define fh_to_ctx(f) (container_of(f, struct hva_ctx, fh))
|
||||
|
||||
#define hva_to_dev(h) (h->dev)
|
||||
|
||||
#define ctx_to_dev(c) (c->hva_dev->dev)
|
||||
|
||||
#define ctx_to_hdev(c) (c->hva_dev)
|
||||
|
||||
#define HVA_PREFIX "[---:----]"
|
||||
|
||||
/**
|
||||
* struct hva_frameinfo - information about hva frame
|
||||
*
|
||||
* @pixelformat: fourcc code for uncompressed video format
|
||||
* @width: width of frame
|
||||
* @height: height of frame
|
||||
* @aligned_width: width of frame (with encoder alignment constraint)
|
||||
* @aligned_height: height of frame (with encoder alignment constraint)
|
||||
* @size: maximum size in bytes required for data
|
||||
*/
|
||||
struct hva_frameinfo {
|
||||
u32 pixelformat;
|
||||
u32 width;
|
||||
u32 height;
|
||||
u32 aligned_width;
|
||||
u32 aligned_height;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hva_streaminfo - information about hva stream
|
||||
*
|
||||
* @streamformat: fourcc code of compressed video format (H.264...)
|
||||
* @width: width of stream
|
||||
* @height: height of stream
|
||||
* @profile: profile string
|
||||
* @level: level string
|
||||
*/
|
||||
struct hva_streaminfo {
|
||||
u32 streamformat;
|
||||
u32 width;
|
||||
u32 height;
|
||||
u8 profile[32];
|
||||
u8 level[32];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hva_controls - hva controls set
|
||||
*
|
||||
* @time_per_frame: time per frame in seconds
|
||||
* @bitrate_mode: bitrate mode (constant bitrate or variable bitrate)
|
||||
* @gop_size: groupe of picture size
|
||||
* @bitrate: bitrate (in bps)
|
||||
* @aspect: video aspect
|
||||
*/
|
||||
struct hva_controls {
|
||||
struct v4l2_fract time_per_frame;
|
||||
enum v4l2_mpeg_video_bitrate_mode bitrate_mode;
|
||||
u32 gop_size;
|
||||
u32 bitrate;
|
||||
enum v4l2_mpeg_video_aspect aspect;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hva_frame - hva frame buffer (output)
|
||||
*
|
||||
* @vbuf: video buffer information for V4L2
|
||||
* @list: V4L2 m2m list that the frame belongs to
|
||||
* @info: frame information (width, height, format, alignment...)
|
||||
* @paddr: physical address (for hardware)
|
||||
* @vaddr: virtual address (kernel can read/write)
|
||||
* @prepared: true if vaddr/paddr are resolved
|
||||
*/
|
||||
struct hva_frame {
|
||||
struct vb2_v4l2_buffer vbuf;
|
||||
struct list_head list;
|
||||
struct hva_frameinfo info;
|
||||
dma_addr_t paddr;
|
||||
void *vaddr;
|
||||
bool prepared;
|
||||
};
|
||||
|
||||
/*
|
||||
* to_hva_frame() - cast struct vb2_v4l2_buffer * to struct hva_frame *
|
||||
*/
|
||||
#define to_hva_frame(vb) \
|
||||
container_of(vb, struct hva_frame, vbuf)
|
||||
|
||||
/**
|
||||
* struct hva_stream - hva stream buffer (capture)
|
||||
*
|
||||
* @v4l2: video buffer information for V4L2
|
||||
* @list: V4L2 m2m list that the frame belongs to
|
||||
* @paddr: physical address (for hardware)
|
||||
* @vaddr: virtual address (kernel can read/write)
|
||||
* @prepared: true if vaddr/paddr are resolved
|
||||
* @size: size of the buffer in bytes
|
||||
* @bytesused: number of bytes occupied by data in the buffer
|
||||
*/
|
||||
struct hva_stream {
|
||||
struct vb2_v4l2_buffer vbuf;
|
||||
struct list_head list;
|
||||
dma_addr_t paddr;
|
||||
void *vaddr;
|
||||
bool prepared;
|
||||
unsigned int size;
|
||||
unsigned int bytesused;
|
||||
};
|
||||
|
||||
/*
|
||||
* to_hva_stream() - cast struct vb2_v4l2_buffer * to struct hva_stream *
|
||||
*/
|
||||
#define to_hva_stream(vb) \
|
||||
container_of(vb, struct hva_stream, vbuf)
|
||||
|
||||
struct hva_dev;
|
||||
struct hva_enc;
|
||||
|
||||
/**
|
||||
* struct hva_ctx - context of hva instance
|
||||
*
|
||||
* @hva_dev: the device that this instance is associated with
|
||||
* @fh: V4L2 file handle
|
||||
* @ctrl_handler: V4L2 controls handler
|
||||
* @ctrls: hva controls set
|
||||
* @id: instance identifier
|
||||
* @aborting: true if current job aborted
|
||||
* @name: instance name (debug purpose)
|
||||
* @run_work: encode work
|
||||
* @lock: mutex used to lock access of this context
|
||||
* @flags: validity of streaminfo and frameinfo fields
|
||||
* @frame_num: frame number
|
||||
* @stream_num: stream number
|
||||
* @max_stream_size: maximum size in bytes required for stream data
|
||||
* @colorspace: colorspace identifier
|
||||
* @xfer_func: transfer function identifier
|
||||
* @ycbcr_enc: Y'CbCr encoding identifier
|
||||
* @quantization: quantization identifier
|
||||
* @streaminfo: stream properties
|
||||
* @frameinfo: frame properties
|
||||
* @enc: current encoder
|
||||
* @priv: private codec data for this instance, allocated
|
||||
* by encoder @open time
|
||||
* @hw_err: true if hardware error detected
|
||||
*/
|
||||
struct hva_ctx {
|
||||
struct hva_dev *hva_dev;
|
||||
struct v4l2_fh fh;
|
||||
struct v4l2_ctrl_handler ctrl_handler;
|
||||
struct hva_controls ctrls;
|
||||
u8 id;
|
||||
bool aborting;
|
||||
char name[100];
|
||||
struct work_struct run_work;
|
||||
/* mutex protecting this data structure */
|
||||
struct mutex lock;
|
||||
u32 flags;
|
||||
u32 frame_num;
|
||||
u32 stream_num;
|
||||
u32 max_stream_size;
|
||||
enum v4l2_colorspace colorspace;
|
||||
enum v4l2_xfer_func xfer_func;
|
||||
enum v4l2_ycbcr_encoding ycbcr_enc;
|
||||
enum v4l2_quantization quantization;
|
||||
struct hva_streaminfo streaminfo;
|
||||
struct hva_frameinfo frameinfo;
|
||||
struct hva_enc *enc;
|
||||
void *priv;
|
||||
bool hw_err;
|
||||
};
|
||||
|
||||
#define HVA_FLAG_STREAMINFO 0x0001
|
||||
#define HVA_FLAG_FRAMEINFO 0x0002
|
||||
|
||||
#define HVA_MAX_INSTANCES 16
|
||||
#define HVA_MAX_ENCODERS 10
|
||||
#define HVA_MAX_FORMATS HVA_MAX_ENCODERS
|
||||
|
||||
/**
|
||||
* struct hva_dev - abstraction for hva entity
|
||||
*
|
||||
* @v4l2_dev: V4L2 device
|
||||
* @vdev: video device
|
||||
* @pdev: platform device
|
||||
* @dev: device
|
||||
* @lock: mutex used for critical sections & V4L2 ops
|
||||
* serialization
|
||||
* @m2m_dev: memory-to-memory V4L2 device information
|
||||
* @instances: opened instances
|
||||
* @nb_of_instances: number of opened instances
|
||||
* @instance_id: rolling counter identifying an instance (debug purpose)
|
||||
* @regs: register io memory access
|
||||
* @esram_addr: esram address
|
||||
* @esram_size: esram size
|
||||
* @clk: hva clock
|
||||
* @irq_its: status interruption
|
||||
* @irq_err: error interruption
|
||||
* @work_queue: work queue to handle the encode jobs
|
||||
* @protect_mutex: mutex used to lock access of hardware
|
||||
* @interrupt: completion interrupt
|
||||
* @ip_version: IP hardware version
|
||||
* @encoders: registered encoders
|
||||
* @nb_of_encoders: number of registered encoders
|
||||
* @pixelformats: supported uncompressed video formats
|
||||
* @nb_of_pixelformats: number of supported umcompressed video formats
|
||||
* @streamformats: supported compressed video formats
|
||||
* @nb_of_streamformats: number of supported compressed video formats
|
||||
* @sfl_reg: status fifo level register value
|
||||
* @sts_reg: status register value
|
||||
* @lmi_err_reg: local memory interface error register value
|
||||
* @emi_err_reg: external memory interface error register value
|
||||
* @hec_mif_err_reg: HEC memory interface error register value
|
||||
*/
|
||||
struct hva_dev {
|
||||
struct v4l2_device v4l2_dev;
|
||||
struct video_device *vdev;
|
||||
struct platform_device *pdev;
|
||||
struct device *dev;
|
||||
/* mutex protecting vb2_queue structure */
|
||||
struct mutex lock;
|
||||
struct v4l2_m2m_dev *m2m_dev;
|
||||
struct hva_ctx *instances[HVA_MAX_INSTANCES];
|
||||
unsigned int nb_of_instances;
|
||||
unsigned int instance_id;
|
||||
void __iomem *regs;
|
||||
u32 esram_addr;
|
||||
u32 esram_size;
|
||||
struct clk *clk;
|
||||
int irq_its;
|
||||
int irq_err;
|
||||
struct workqueue_struct *work_queue;
|
||||
/* mutex protecting hardware access */
|
||||
struct mutex protect_mutex;
|
||||
struct completion interrupt;
|
||||
unsigned long int ip_version;
|
||||
const struct hva_enc *encoders[HVA_MAX_ENCODERS];
|
||||
u32 nb_of_encoders;
|
||||
u32 pixelformats[HVA_MAX_FORMATS];
|
||||
u32 nb_of_pixelformats;
|
||||
u32 streamformats[HVA_MAX_FORMATS];
|
||||
u32 nb_of_streamformats;
|
||||
u32 sfl_reg;
|
||||
u32 sts_reg;
|
||||
u32 lmi_err_reg;
|
||||
u32 emi_err_reg;
|
||||
u32 hec_mif_err_reg;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hva_enc - hva encoder
|
||||
*
|
||||
* @name: encoder name
|
||||
* @streamformat: fourcc code for compressed video format (H.264...)
|
||||
* @pixelformat: fourcc code for uncompressed video format
|
||||
* @max_width: maximum width of frame for this encoder
|
||||
* @max_height: maximum height of frame for this encoder
|
||||
* @open: open encoder
|
||||
* @close: close encoder
|
||||
* @encode: encode a frame (struct hva_frame) in a stream
|
||||
* (struct hva_stream)
|
||||
*/
|
||||
|
||||
struct hva_enc {
|
||||
const char *name;
|
||||
u32 streamformat;
|
||||
u32 pixelformat;
|
||||
u32 max_width;
|
||||
u32 max_height;
|
||||
int (*open)(struct hva_ctx *ctx);
|
||||
int (*close)(struct hva_ctx *ctx);
|
||||
int (*encode)(struct hva_ctx *ctx, struct hva_frame *frame,
|
||||
struct hva_stream *stream);
|
||||
};
|
||||
|
||||
#endif /* HVA_H */
|
||||
Loading…
Reference in New Issue