Renesas ARM Based SoC Updates for v3.15
* r7s72100 SoC (RZ/A1H) - Add i2c clocks (portion missing from previous patch due to miss-merge) * r8a7791 (R-Car M2) - Add SATA clocks - Add ZS clock - Wait for status on all MSTP clocks -- Add I2C and VIN clocks * r8a7790 (R-Car H2) - Add PCI USB host clock support - Add Audio DMAC, SATA and VIN clocks - Add Audio DMAC support * r8a7779 (R-Car H1) - Wait for status on selected MSTP clocks -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJS8yO9AAoJENfPZGlqN0++nzMP/RR48DSawwNaFusAjNbeAZz1 OxmcXefuy1WOBgH0yW94VYsC2aulssNq9LXciGGE/uTjbXth7cV65tyHbfp73BCr xMeFhmWbRtUZ17uq1QEckevQjEy/KAtADzXSY2bbIjIBXtBRCW2L8aTAVbNYYXZl Etltuta+BZggwlCQjZ3Z/lct25rB5aZMQWTRtp2rHSh+EayYgxMgY4AXw5gByEE6 xWQO+9uKKaLisE0clzDTZ3gFahJsaBVtyvDKq4olYZGtFrnqOilb22JTs6g0+W3+ iiAPHeeonAI5RP5Vyw35vaFJyVZ85Qoa49zBqQPvkrs1LXC+FPGLpFnHn4aTDK15 nxGnmilVMhgI3yhrSGBj6qne584dctP103uVhe1CBULWx0T3fcWOK4FZPqLAJyty fr35u2QIAn1LRXPsqx+vzRle7iwS7oYwrjw9kvBRj0XRMd/XVabb/Po094VeQ7rZ rO+64ssESC1eb6qxyQJIPIRQO8qANeV0pc3XBV+5fVhI+rSBaUonH0OYNd3fXxMb V+EFpNkDOX7f7lIzpOxZmYTmCQ3K1ESzbhjP3zkUZqy2YRqWdz64uDTgk0zHvBh2 ijKoohb+FlG8YKeZQU1nRiID3X4dZLTeXurBu4/xFVAh95JC3OWNrmeueip3yxJv uYWnHcvZIV3J3/gvc5Ly =T5hu -----END PGP SIGNATURE----- Merge tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Merge "Renesas ARM Based SoC Updates for v3.15" from Simon Horman: * r7s72100 SoC (RZ/A1H) - Add i2c clocks (portion missing from previous patch due to miss-merge) * r8a7791 (R-Car M2) - Add SATA clocks - Add ZS clock - Wait for status on all MSTP clocks -- Add I2C and VIN clocks * r8a7790 (R-Car H2) - Add PCI USB host clock support - Add Audio DMAC, SATA and VIN clocks - Add Audio DMAC support * r8a7779 (R-Car H1) - Wait for status on selected MSTP clocks * tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: Add PCI USB host clock support ARM: shmobile: r7s72100: really add i2c clocks ARM: shmobile: r8a7791: Add SATA clocks ARM: shmobile: r8a7791: Add ZS clock ARM: shmobile: r8a7790: Add SATA clocks ARM: shmobile: r8a7790: Add VIN clock support ARM: shmobile: r8a7790: add Audio DMAC support ARM: shmobile: r8a7790: add Audio DMAC clock ARM: shmobile: r8a7791: Wait for status on all MSTP clocks ARM: shmobile: r8a7791: Add VIN clocks ARM: shmobile: r8a7791: Add I2C clocks ARM: shmobile: r8a7790: Wait for status on all MSTP clocks ARM: shmobile: r8a7779: Wait for status on selected MSTP clocks ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
This commit is contained in:
Olof Johansson
commit
58035fcc94
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@ -176,6 +176,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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/* MSTP clocks */
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CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
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CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
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CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
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CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
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CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
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/* ICK */
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@ -127,16 +127,16 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
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[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
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[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
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[MSTP120] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 20, 0), /* VIN3 */
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[MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
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[MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
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[MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
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[MSTP110] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 10, 0), /* VIN0 */
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[MSTP109] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 9, 0), /* VIN1 */
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[MSTP108] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 8, 0), /* VIN2 */
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[MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
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[MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */
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[MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */
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[MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */
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[MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */
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[MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */
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[MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */
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[MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */
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[MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 9, MSTPSR1, 0), /* VIN1 */
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[MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 8, MSTPSR1, 0), /* VIN2 */
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[MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 3, MSTPSR1, 0), /* DU */
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[MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 1, MSTPSR1, 0), /* USB2 */
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[MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 0, MSTPSR1, 0), /* USB0/1 */
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[MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
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[MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
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[MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
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@ -43,17 +43,26 @@
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* see "p1 / 2" on R8A7790_CLOCK_ROOT() below
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*/
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x1000
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x1000
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#define SMSTPCR1 0xe6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR5 0xe6150144
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#define SMSTPCR7 0xe615014c
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#define SMSTPCR8 0xe6150990
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#define SMSTPCR9 0xe6150994
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#define SMSTPCR10 0xe6150998
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#define SMSTPCR1 0xe6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR5 0xe6150144
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#define SMSTPCR7 0xe615014c
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#define SMSTPCR8 0xe6150990
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#define SMSTPCR9 0xe6150994
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#define SMSTPCR10 0xe6150998
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#define MSTPSR1 IOMEM(0xe6150038)
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#define MSTPSR2 IOMEM(0xe6150040)
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#define MSTPSR3 IOMEM(0xe6150048)
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#define MSTPSR5 IOMEM(0xe615003c)
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#define MSTPSR7 IOMEM(0xe61501c4)
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#define MSTPSR8 IOMEM(0xe61509a0)
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#define MSTPSR9 IOMEM(0xe61509a4)
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#define MSTPSR10 IOMEM(0xe61509a8)
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#define SDCKCR 0xE6150074
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#define SD2CKCR 0xE6150078
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@ -187,11 +196,14 @@ enum {
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MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
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MSTP931, MSTP930, MSTP929, MSTP928,
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MSTP917,
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MSTP815, MSTP814,
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MSTP813,
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MSTP811, MSTP810, MSTP809, MSTP808,
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MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
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MSTP717, MSTP716,
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MSTP704,
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MSTP704, MSTP703,
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MSTP522,
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MSTP502, MSTP501,
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MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
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MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
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MSTP124,
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@ -199,48 +211,57 @@ enum {
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */
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[MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */
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[MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */
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[MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */
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[MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */
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[MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */
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[MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */
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[MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */
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[MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */
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[MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */
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[MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */
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[MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
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[MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
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[MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
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[MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
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[MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
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[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
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[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
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[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
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[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
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[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
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[MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */
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[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
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[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
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[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
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[MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
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[MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */
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[MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
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[MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
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[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
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[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
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[MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */
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[MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */
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[MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */
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[MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
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[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
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[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
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[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
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[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
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[MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
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[MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
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[MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
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[MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
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[MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
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[MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
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[MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
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[MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
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[MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
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[MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
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[MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
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[MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
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[MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
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[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
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[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
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[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
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[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
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[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
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[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
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[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
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[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
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[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
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[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
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[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
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[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
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[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
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[MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
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[MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
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[MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
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[MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
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[MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
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[MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
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[MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
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[MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
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[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
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[MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
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[MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
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[MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
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[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
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[MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
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[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
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[MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
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[MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
|
||||
[MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
|
||||
[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
|
||||
[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
|
||||
[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
|
||||
[MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
|
||||
[MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
|
||||
[MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
|
|
@ -300,8 +321,14 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
|
||||
CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
|
||||
CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
|
||||
CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
|
||||
CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
|
||||
CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
|
||||
CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
|
||||
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
|
||||
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
|
||||
CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
|
||||
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
|
||||
CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
|
||||
|
|
@ -317,6 +344,11 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
|
||||
CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
|
||||
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
|
||||
CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
|
||||
CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
|
||||
CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
|
||||
CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
|
||||
CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
|
||||
|
||||
/* ICK */
|
||||
CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
|
||||
|
|
|
|||
|
|
@ -59,6 +59,14 @@
|
|||
#define SMSTPCR10 0xE6150998
|
||||
#define SMSTPCR11 0xE615099C
|
||||
|
||||
#define MSTPSR1 IOMEM(0xe6150038)
|
||||
#define MSTPSR2 IOMEM(0xe6150040)
|
||||
#define MSTPSR5 IOMEM(0xe615003c)
|
||||
#define MSTPSR7 IOMEM(0xe61501c4)
|
||||
#define MSTPSR8 IOMEM(0xe61509a0)
|
||||
#define MSTPSR9 IOMEM(0xe61509a4)
|
||||
#define MSTPSR11 IOMEM(0xe61509ac)
|
||||
|
||||
#define MODEMR 0xE6160060
|
||||
#define SDCKCR 0xE6150074
|
||||
#define SD2CKCR 0xE6150078
|
||||
|
|
@ -103,7 +111,9 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
|
|||
SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
|
||||
SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
|
||||
SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
|
||||
SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
|
||||
SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
|
||||
SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&extal_clk,
|
||||
|
|
@ -117,12 +127,17 @@ static struct clk *main_clks[] = {
|
|||
&rclk_clk,
|
||||
&mp_clk,
|
||||
&cp_clk,
|
||||
&zg_clk,
|
||||
&zx_clk,
|
||||
&zs_clk,
|
||||
};
|
||||
|
||||
/* MSTP */
|
||||
enum {
|
||||
MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
|
||||
MSTP815, MSTP814,
|
||||
MSTP813,
|
||||
MSTP811, MSTP810, MSTP809,
|
||||
MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
|
||||
MSTP719, MSTP718, MSTP715, MSTP714,
|
||||
MSTP522,
|
||||
|
|
@ -133,27 +148,38 @@ enum {
|
|||
};
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
|
||||
[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
|
||||
[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
|
||||
[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
|
||||
[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
|
||||
[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
|
||||
[MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
|
||||
[MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
|
||||
[MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
|
||||
[MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
|
||||
[MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
|
||||
[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
|
||||
[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
|
||||
[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
|
||||
[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
|
||||
[MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */
|
||||
[MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */
|
||||
[MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */
|
||||
[MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
|
||||
[MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
|
||||
[MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
|
||||
[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
|
||||
[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
|
||||
[MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
|
||||
[MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
|
||||
[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
|
||||
[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
|
||||
[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
|
||||
[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
|
||||
[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
|
||||
[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
|
||||
[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
|
||||
[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
|
||||
[MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
|
||||
[MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
|
||||
[MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
|
||||
[MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */
|
||||
[MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
|
||||
[MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
|
||||
[MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
|
||||
[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
|
||||
[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
|
||||
[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
|
||||
[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
|
||||
[MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
|
||||
[MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
|
||||
[MSTP1105] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 5, MSTPSR11, 0), /* SCIFA3 */
|
||||
[MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA4 */
|
||||
[MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA5 */
|
||||
[MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
|
|
@ -165,6 +191,8 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_CON_ID("pll1", &pll1_clk),
|
||||
CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
|
||||
CLKDEV_CON_ID("pll3", &pll3_clk),
|
||||
CLKDEV_CON_ID("zg", &zg_clk),
|
||||
CLKDEV_CON_ID("zs", &zs_clk),
|
||||
CLKDEV_CON_ID("hp", &hp_clk),
|
||||
CLKDEV_CON_ID("p", &p_clk),
|
||||
CLKDEV_CON_ID("rclk", &rclk_clk),
|
||||
|
|
@ -194,7 +222,18 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
|
||||
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
|
||||
CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
|
||||
CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
|
||||
CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
|
||||
CLKDEV_DEV_ID("i2c-rcar_gen2.4", &mstp_clks[MSTP927]),
|
||||
CLKDEV_DEV_ID("i2c-rcar_gen2.5", &mstp_clks[MSTP925]),
|
||||
CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
|
||||
CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),
|
||||
CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),
|
||||
CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
|
||||
CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
|
||||
CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
|
||||
};
|
||||
|
||||
#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
|
||||
|
|
|
|||
|
|
@ -3,6 +3,31 @@
|
|||
|
||||
#include <mach/rcar-gen2.h>
|
||||
|
||||
/* DMA slave IDs */
|
||||
enum {
|
||||
RCAR_DMA_SLAVE_INVALID,
|
||||
AUDIO_DMAC_SLAVE_SSI0_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI0_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI1_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI1_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI2_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI2_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI3_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI3_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI4_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI4_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI5_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI5_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI6_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI6_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI7_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI7_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI8_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI8_RX,
|
||||
AUDIO_DMAC_SLAVE_SSI9_TX,
|
||||
AUDIO_DMAC_SLAVE_SSI9_RX,
|
||||
};
|
||||
|
||||
void r8a7790_add_standard_devices(void);
|
||||
void r8a7790_add_dt_devices(void);
|
||||
void r8a7790_clock_init(void);
|
||||
|
|
|
|||
|
|
@ -24,12 +24,100 @@
|
|||
#include <linux/platform_data/gpio-rcar.h>
|
||||
#include <linux/platform_data/irq-renesas-irqc.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_dma.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/dma-register.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a7790.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
/* Audio-DMAC */
|
||||
#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
|
||||
{ \
|
||||
.slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
|
||||
.addr = _addr + 0x8, \
|
||||
.chcr = CHCR_TX(XMIT_SZ_32BIT), \
|
||||
.mid_rid = t, \
|
||||
}, { \
|
||||
.slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
|
||||
.addr = _addr + 0xc, \
|
||||
.chcr = CHCR_RX(XMIT_SZ_32BIT), \
|
||||
.mid_rid = r, \
|
||||
}
|
||||
|
||||
static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
|
||||
AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
|
||||
AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
|
||||
AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
|
||||
AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
|
||||
AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
|
||||
AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
|
||||
AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
|
||||
AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
|
||||
AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
|
||||
AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
|
||||
};
|
||||
|
||||
#define DMAE_CHANNEL(a, b) \
|
||||
{ \
|
||||
.offset = (a) - 0x20, \
|
||||
.dmars = (a) - 0x20 + 0x40, \
|
||||
.chclr_bit = (b), \
|
||||
.chclr_offset = 0x80 - 0x20, \
|
||||
}
|
||||
|
||||
static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
|
||||
DMAE_CHANNEL(0x8000, 0),
|
||||
DMAE_CHANNEL(0x8080, 1),
|
||||
DMAE_CHANNEL(0x8100, 2),
|
||||
DMAE_CHANNEL(0x8180, 3),
|
||||
DMAE_CHANNEL(0x8200, 4),
|
||||
DMAE_CHANNEL(0x8280, 5),
|
||||
DMAE_CHANNEL(0x8300, 6),
|
||||
DMAE_CHANNEL(0x8380, 7),
|
||||
DMAE_CHANNEL(0x8400, 8),
|
||||
DMAE_CHANNEL(0x8480, 9),
|
||||
DMAE_CHANNEL(0x8500, 10),
|
||||
DMAE_CHANNEL(0x8580, 11),
|
||||
DMAE_CHANNEL(0x8600, 12),
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
|
||||
.slave = r8a7790_audio_dmac_slaves,
|
||||
.slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
|
||||
.channel = r8a7790_audio_dmac_channels,
|
||||
.channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
|
||||
.ts_low_shift = TS_LOW_SHIFT,
|
||||
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
|
||||
.ts_high_shift = TS_HI_SHIFT,
|
||||
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
|
||||
.ts_shift = dma_ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
|
||||
.dmaor_init = DMAOR_DME,
|
||||
.chclr_present = 1,
|
||||
.chclr_bitwise = 1,
|
||||
};
|
||||
|
||||
static struct resource r8a7790_audio_dmac_resources[] = {
|
||||
/* Channel registers and DMAOR for low */
|
||||
DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
|
||||
DEFINE_RES_IRQ(gic_spi(346)),
|
||||
DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
|
||||
|
||||
/* Channel registers and DMAOR for hi */
|
||||
DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
|
||||
DEFINE_RES_IRQ(gic_spi(347)),
|
||||
DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
|
||||
};
|
||||
|
||||
#define r8a7790_register_audio_dmac(id) \
|
||||
platform_device_register_resndata( \
|
||||
&platform_bus, "sh-dma-engine", id, \
|
||||
&r8a7790_audio_dmac_resources[id * 3], 3, \
|
||||
&r8a7790_audio_dmac_platform_data, \
|
||||
sizeof(r8a7790_audio_dmac_platform_data))
|
||||
|
||||
static const struct resource pfc_resources[] __initconst = {
|
||||
DEFINE_RES_MEM(0xe6060000, 0x250),
|
||||
};
|
||||
|
|
@ -101,6 +189,8 @@ void __init r8a7790_pinmux_init(void)
|
|||
r8a7790_register_i2c(1);
|
||||
r8a7790_register_i2c(2);
|
||||
r8a7790_register_i2c(3);
|
||||
r8a7790_register_audio_dmac(0);
|
||||
r8a7790_register_audio_dmac(1);
|
||||
}
|
||||
|
||||
#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
|
||||
|
|
|
|||
|
|
@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk)
|
|||
iowrite32(value, clk->mapped_reg);
|
||||
}
|
||||
|
||||
static unsigned int r8(const void __iomem *addr)
|
||||
{
|
||||
return ioread8(addr);
|
||||
}
|
||||
|
||||
static unsigned int r16(const void __iomem *addr)
|
||||
{
|
||||
return ioread16(addr);
|
||||
}
|
||||
|
||||
static unsigned int r32(const void __iomem *addr)
|
||||
{
|
||||
return ioread32(addr);
|
||||
}
|
||||
|
||||
static int sh_clk_mstp_enable(struct clk *clk)
|
||||
{
|
||||
sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
|
||||
if (clk->status_reg) {
|
||||
unsigned int (*read)(const void __iomem *addr);
|
||||
int i;
|
||||
void __iomem *mapped_status = (phys_addr_t)clk->status_reg -
|
||||
(phys_addr_t)clk->enable_reg + clk->mapped_reg;
|
||||
|
||||
if (clk->flags & CLK_ENABLE_REG_8BIT)
|
||||
read = r8;
|
||||
else if (clk->flags & CLK_ENABLE_REG_16BIT)
|
||||
read = r16;
|
||||
else
|
||||
read = r32;
|
||||
|
||||
for (i = 1000;
|
||||
(read(mapped_status) & (1 << clk->enable_bit)) && i;
|
||||
i--)
|
||||
cpu_relax();
|
||||
if (!i) {
|
||||
pr_err("cpg: failed to enable %p[%d]\n",
|
||||
clk->enable_reg, clk->enable_bit);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ struct clk {
|
|||
unsigned long flags;
|
||||
|
||||
void __iomem *enable_reg;
|
||||
void __iomem *status_reg;
|
||||
unsigned int enable_bit;
|
||||
void __iomem *mapped_reg;
|
||||
|
||||
|
|
@ -116,22 +117,26 @@ long clk_round_parent(struct clk *clk, unsigned long target,
|
|||
unsigned long *best_freq, unsigned long *parent_freq,
|
||||
unsigned int div_min, unsigned int div_max);
|
||||
|
||||
#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
|
||||
#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
|
||||
{ \
|
||||
.parent = _parent, \
|
||||
.enable_reg = (void __iomem *)_enable_reg, \
|
||||
.enable_bit = _enable_bit, \
|
||||
.status_reg = _status_reg, \
|
||||
.flags = _flags, \
|
||||
}
|
||||
|
||||
#define SH_CLK_MSTP32(_p, _r, _b, _f) \
|
||||
SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
|
||||
#define SH_CLK_MSTP32(_p, _r, _b, _f) \
|
||||
SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
|
||||
|
||||
#define SH_CLK_MSTP16(_p, _r, _b, _f) \
|
||||
SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
|
||||
#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
|
||||
SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
|
||||
|
||||
#define SH_CLK_MSTP8(_p, _r, _b, _f) \
|
||||
SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
|
||||
#define SH_CLK_MSTP16(_p, _r, _b, _f) \
|
||||
SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
|
||||
|
||||
#define SH_CLK_MSTP8(_p, _r, _b, _f) \
|
||||
SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
|
||||
|
||||
int sh_clk_mstp_register(struct clk *clks, int nr);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue