[PATCH] gxfb: Turn on the flatpanel power and data

For Geode devices without a flatpanel aware BIOS, this enables the flatpanel
power and data.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Acked-by: James Simmons <jsimmons@infradead.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Jordan Crouse 2006-12-08 02:40:56 -08:00 committed by Linus Torvalds
parent 53d53bd4ab
commit 58219896df
2 changed files with 13 additions and 2 deletions

View file

@ -220,7 +220,13 @@ gx_configure_tft(struct fb_info *info)
/* Set the dither control */ /* Set the dither control */
writel(0x70, par->vid_regs + GX_FP_DFC); writel(0x70, par->vid_regs + GX_FP_DFC);
/* Turn on the device */ /* Enable the FP data and power (in case the BIOS didn't) */
fp = readl(par->vid_regs + GX_DCFG);
fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN;
writel(fp, par->vid_regs + GX_DCFG);
/* Unblank the panel */
fp = readl(par->vid_regs + GX_FP_PM); fp = readl(par->vid_regs + GX_FP_PM);
fp |= GX_FP_PM_P; fp |= GX_FP_PM_P;
@ -245,9 +251,12 @@ static void gx_configure_display(struct fb_info *info)
writel(misc, par->vid_regs + GX_MISC); writel(misc, par->vid_regs + GX_MISC);
/* Write the display configuration */ /* Write the display configuration */
dcfg = readl(par->vid_regs + GX_DCFG); dcfg = readl(par->vid_regs + GX_DCFG);
/* Disable hsync and vsync */
dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
writel(dcfg, par->vid_regs + GX_DCFG);
/* Clear bits from existing mode. */ /* Clear bits from existing mode. */
dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
| GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL

View file

@ -25,6 +25,8 @@ extern struct geode_vid_ops gx_vid_ops;
# define GX_DCFG_HSYNC_EN 0x00000002 # define GX_DCFG_HSYNC_EN 0x00000002
# define GX_DCFG_VSYNC_EN 0x00000004 # define GX_DCFG_VSYNC_EN 0x00000004
# define GX_DCFG_DAC_BL_EN 0x00000008 # define GX_DCFG_DAC_BL_EN 0x00000008
# define GX_DCFG_FP_PWR_EN 0x00000040
# define GX_DCFG_FP_DATA_EN 0x00000080
# define GX_DCFG_CRT_HSYNC_POL 0x00000100 # define GX_DCFG_CRT_HSYNC_POL 0x00000100
# define GX_DCFG_CRT_VSYNC_POL 0x00000200 # define GX_DCFG_CRT_VSYNC_POL 0x00000200
# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 # define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000