smsc911x: enforce read-after-write timing restriction on eeprom access
The LAN911x datasheet specifies a minimum delay of 45ns between a write of E2P_DATA and any read. This patch adds a single dummy read of BYTE_TEST to enforce this timing constraint. Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1680,6 +1680,7 @@ static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
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u8 address, u8 data)
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{
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u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
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u32 temp;
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int ret;
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SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
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@ -1688,6 +1689,10 @@ static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
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if (!ret) {
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op = E2P_CMD_EPC_CMD_WRITE_ | address;
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smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
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/* Workaround for hardware read-after-write restriction */
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temp = smsc911x_reg_read(pdata, BYTE_TEST);
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ret = smsc911x_eeprom_send_cmd(pdata, op);
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}
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