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MLK-19114-2 gpu: imx: imx8-prefetch: Remove has_prefetech_fixup from devtypes 

There are prefetch engine fixups embedded in the updated i.MX8QM silicons.
So, prefetch engines in all i.MX8 variants should be the same.  Let's
remove has_prefetech_fixup from devtypes which is no more needed.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 875c31a70f3527c59cc597a10a88c39f3a0095df)
pull/10/head
Liu Ying 2018-08-02 13:55:34 +08:00 committed by Jason Liu
parent 793acb14a1
commit 5914815026
8 changed files with 31 additions and 109 deletions
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10
drivers/gpu/drm/imx/dpu/dpu-crtc.c
View File

@ -47,8 +47,6 @@ struct dpu_crtc {
int content_shdld_irq;
int dec_shdld_irq;
bool has_prefetch_fixup;
struct completion safety_shdld_done;
struct completion content_shdld_done;
struct completion dec_shdld_done;
@ -628,14 +626,12 @@ static int dpu_crtc_init(struct dpu_crtc *dpu_crtc,
struct drm_crtc *crtc = &dpu_crtc->base;
struct dpu_plane_grp *plane_grp = pdata->plane_grp;
unsigned int stream_id = pdata->stream_id;
bool has_prefetch_fixup = dpu_has_prefetch_fixup(dpu);
int i, ret;
init_completion(&dpu_crtc->safety_shdld_done);
init_completion(&dpu_crtc->content_shdld_done);
init_completion(&dpu_crtc->dec_shdld_done);
dpu_crtc->has_prefetch_fixup = has_prefetch_fixup;
dpu_crtc->stream_id = stream_id;
dpu_crtc->hw_plane_num = plane_grp->hw_plane_num;
@ -652,8 +648,7 @@ static int dpu_crtc_init(struct dpu_crtc *dpu_crtc,
plane_grp->res.fg[stream_id] = dpu_crtc->fg;
dpu_crtc->plane[0] = dpu_plane_init(drm, 0, stream_id, plane_grp,
DRM_PLANE_TYPE_PRIMARY,
has_prefetch_fixup);
DRM_PLANE_TYPE_PRIMARY);
if (IS_ERR(dpu_crtc->plane[0])) {
ret = PTR_ERR(dpu_crtc->plane[0]);
dev_err(dev, "initializing plane0 failed with %d.\n", ret);
@ -673,8 +668,7 @@ static int dpu_crtc_init(struct dpu_crtc *dpu_crtc,
dpu_crtc->plane[i] = dpu_plane_init(drm,
drm_crtc_mask(&dpu_crtc->base),
stream_id, plane_grp,
DRM_PLANE_TYPE_OVERLAY,
has_prefetch_fixup);
DRM_PLANE_TYPE_OVERLAY);
if (IS_ERR(dpu_crtc->plane[i])) {
ret = PTR_ERR(dpu_crtc->plane[i]);
dev_err(dev, "initializing plane%d failed with %d.\n",

8
drivers/gpu/drm/imx/dpu/dpu-plane.c
View File

@ -272,10 +272,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
fb->modifier != DRM_FORMAT_MOD_VIVANTE_SUPER_TILED)
return -EINVAL;
if (fb->modifier && (src_x || src_y) &&
!dplane->has_prefetch_fixup)
return -EINVAL;
if (dplane->grp->has_vproc) {
/* no down scaling */
if (src_w > state->crtc_w || src_h > state->crtc_h)
@ -720,8 +716,7 @@ struct dpu_plane *dpu_plane_init(struct drm_device *drm,
unsigned int possible_crtcs,
unsigned int stream_id,
struct dpu_plane_grp *grp,
enum drm_plane_type type,
bool has_prefetch_fixup)
enum drm_plane_type type)
{
struct dpu_plane *dpu_plane;
struct drm_plane *plane;
@ -734,7 +729,6 @@ struct dpu_plane *dpu_plane_init(struct drm_device *drm,
dpu_plane->stream_id = stream_id;
dpu_plane->grp = grp;
dpu_plane->has_prefetch_fixup = has_prefetch_fixup;
plane = &dpu_plane->base;

4
drivers/gpu/drm/imx/dpu/dpu-plane.h
View File

@ -31,7 +31,6 @@ struct dpu_plane {
struct dpu_plane_grp *grp;
struct list_head head;
unsigned int stream_id;
bool has_prefetch_fixup;
};
struct dpu_plane_state {
@ -191,6 +190,5 @@ struct dpu_plane *dpu_plane_init(struct drm_device *drm,
unsigned int possible_crtcs,
unsigned int stream_id,
struct dpu_plane_grp *grp,
enum drm_plane_type type,
bool has_prefetch_fixup);
enum drm_plane_type type);
#endif

9
drivers/gpu/imx/dpu/dpu-common.c
View File

@ -542,7 +542,6 @@ static const struct dpu_devtype dpu_type_v1 = {
.plane_src_na_mask = 0xffffff80,
.has_capture = true,
.has_prefetch = false,
.has_prefetch_fixup = false,
.has_disp_sel_clk = false,
.has_dual_ldb = false,
.pixel_link_quirks = false,
@ -573,7 +572,6 @@ static const struct dpu_devtype dpu_type_v2_qm = {
.plane_src_na_mask = 0xffffffe2,
.has_capture = false,
.has_prefetch = true,
.has_prefetch_fixup = false,
.has_disp_sel_clk = true,
.has_dual_ldb = false,
.pixel_link_quirks = true,
@ -604,7 +602,6 @@ static const struct dpu_devtype dpu_type_v2_qxp = {
.plane_src_na_mask = 0xffffffe2,
.has_capture = false,
.has_prefetch = true,
.has_prefetch_fixup = true,
.has_disp_sel_clk = false,
.has_dual_ldb = true,
.pixel_link_quirks = true,
@ -625,12 +622,6 @@ static const struct of_device_id dpu_dt_ids[] = {
};
MODULE_DEVICE_TABLE(of, dpu_dt_ids);
bool dpu_has_prefetch_fixup(struct dpu_soc *dpu)
{
return dpu->devtype->has_prefetch_fixup;
}
EXPORT_SYMBOL_GPL(dpu_has_prefetch_fixup);
bool dpu_vproc_has_fetcheco_cap(u32 cap_mask)
{
return !!(cap_mask & DPU_VPROC_CAP_FETCHECO);

1
drivers/gpu/imx/dpu/dpu-prv.h
View File

@ -207,7 +207,6 @@ struct dpu_devtype {
const u32 plane_src_na_mask;
bool has_capture;
bool has_prefetch;
bool has_prefetch_fixup;
bool has_disp_sel_clk;
bool has_dual_ldb;
bool pixel_link_quirks;

75
drivers/gpu/imx/imx8_dprc.c
View File

@ -146,21 +146,8 @@ enum {
#define ROWS_0_6 BIT(0)
#define ROWS_0_4 0
struct dprc_devtype {
bool has_fixup;
};
static const struct dprc_devtype dprc_type_v1 = {
.has_fixup = false,
};
static const struct dprc_devtype dprc_type_v2 = {
.has_fixup = true,
};
struct dprc {
struct device *dev;
const struct dprc_devtype *devtype;
void __iomem *base;
struct list_head list;
struct clk *clk_apb;
@ -410,34 +397,23 @@ void dprc_configure(struct dprc *dprc, unsigned int stream_id,
preq = modifier ? BYTE_64 : BYTE_1K;
dprc_write(dprc, preq, FRAME_2P_CTRL0);
if (!dprc->devtype->has_fixup) {
dprc_write(dprc,
NUM_X_PIX_WIDE(p2_w), FRAME_2P_PIX_X_CTRL);
dprc_write(dprc,
NUM_Y_PIX_HIGH(p2_h), FRAME_2P_PIX_Y_CTRL);
} else {
if (dprc->sc_resource == SC_R_DC_0_BLIT1) {
dprc_prg_sel_configure(dprc,
SC_R_DC_0_BLIT0, true);
prg_set_auxiliary(dprc->prgs[1]);
dprc->has_aux_prg = true;
}
if (dprc->sc_resource == SC_R_DC_0_BLIT1) {
dprc_prg_sel_configure(dprc, SC_R_DC_0_BLIT0, true);
prg_set_auxiliary(dprc->prgs[1]);
dprc->has_aux_prg = true;
}
dprc_write(dprc, uv_baddr, FRAME_2P_BASE_ADDR_CTRL0);
} else {
if (dprc->devtype->has_fixup) {
switch (dprc->sc_resource) {
case SC_R_DC_0_BLIT0:
dprc_prg_sel_configure(dprc,
SC_R_DC_0_BLIT0, false);
prg_set_primary(dprc->prgs[0]);
break;
case SC_R_DC_0_BLIT1:
dprc->has_aux_prg = false;
break;
default:
break;
}
switch (dprc->sc_resource) {
case SC_R_DC_0_BLIT0:
dprc_prg_sel_configure(dprc, SC_R_DC_0_BLIT0, false);
prg_set_primary(dprc->prgs[0]);
break;
case SC_R_DC_0_BLIT1:
dprc->has_aux_prg = false;
break;
default:
break;
}
switch (modifier) {
@ -445,7 +421,7 @@ void dprc_configure(struct dprc *dprc, unsigned int stream_id,
p1_w = round_up(dprc_width, info->cpp[0] == 2 ? 8 : 4);
break;
case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED:
if (dprc->is_blit_chan && dprc->devtype->has_fixup)
if (dprc->is_blit_chan)
p1_w = round_up(dprc_width,
info->cpp[0] == 2 ? 8 : 4);
else
@ -472,10 +448,7 @@ void dprc_configure(struct dprc *dprc, unsigned int stream_id,
preq = BYTE_64;
mt_w = 8;
} else {
if (dprc->devtype->has_fixup)
preq = (x_offset % 8) ? BYTE_64 : BYTE_128;
else
preq = BYTE_128;
preq = (x_offset % 8) ? BYTE_64 : BYTE_128;
mt_w = 4;
}
mt_h = 4;
@ -488,7 +461,7 @@ void dprc_configure(struct dprc *dprc, unsigned int stream_id,
dprc_write(dprc, NUM_X_PIX_WIDE(p1_w), FRAME_1P_PIX_X_CTRL);
dprc_write(dprc, NUM_Y_PIX_HIGH(p1_h), FRAME_1P_PIX_Y_CTRL);
dprc_write(dprc, baddr, FRAME_1P_BASE_ADDR_CTRL0);
if (dprc->devtype->has_fixup && modifier) {
if (modifier) {
dprc_write(dprc, CROP_ULC_X(round_down(x_offset, mt_w)),
FRAME_PIX_X_ULC_CTRL);
dprc_write(dprc, CROP_ULC_Y(round_down(y_offset, mt_h)),
@ -719,9 +692,6 @@ bool dprc_format_supported(struct dprc *dprc, u32 format, u64 modifier)
case SC_R_DC_1_WARP:
return false;
case SC_R_DC_0_BLIT1:
if (!dprc->devtype->has_fixup)
break;
return (modifier == DRM_FORMAT_MOD_NONE ||
modifier == DRM_FORMAT_MOD_AMPHION_TILED);
}
@ -801,15 +771,13 @@ dprc_lookup_by_phandle(struct device *dev, const char *name, int index)
EXPORT_SYMBOL_GPL(dprc_lookup_by_phandle);
static const struct of_device_id dprc_dt_ids[] = {
{ .compatible = "fsl,imx8qm-dpr-channel", .data = &dprc_type_v1, },
{ .compatible = "fsl,imx8qxp-dpr-channel", .data = &dprc_type_v2, },
{ .compatible = "fsl,imx8qm-dpr-channel", },
{ .compatible = "fsl,imx8qxp-dpr-channel", },
{ /* sentinel */ },
};
static int dprc_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
of_match_device(dprc_dt_ids, &pdev->dev);
struct device *dev = &pdev->dev;
struct resource *res;
struct dprc *dprc;
@ -819,8 +787,6 @@ static int dprc_probe(struct platform_device *pdev)
if (!dprc)
return -ENOMEM;
dprc->devtype = of_id->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dprc->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(dprc->base))
@ -850,8 +816,7 @@ static int dprc_probe(struct platform_device *pdev)
switch (dprc->sc_resource) {
case SC_R_DC_0_BLIT1:
if (dprc->devtype->has_fixup)
dprc->has_aux_prg = true;
dprc->has_aux_prg = true;
/* fall-through */
case SC_R_DC_0_BLIT0:
case SC_R_DC_1_BLIT0:

31
drivers/gpu/imx/imx8_prg.c
View File

@ -67,21 +67,8 @@ enum {
#define PRG_WIDTH 0x70
#define WIDTH(n) (((n) - 1) & 0xffff)
struct prg_devtype {
bool has_dprc_fixup;
};
static const struct prg_devtype prg_type_v1 = {
.has_dprc_fixup = false,
};
static const struct prg_devtype prg_type_v2 = {
.has_dprc_fixup = true,
};
struct prg {
struct device *dev;
const struct prg_devtype *devtype;
void __iomem *base;
struct list_head list;
struct clk *clk_apb;
@ -163,7 +150,7 @@ void prg_configure(struct prg *prg, unsigned int width, unsigned int height,
return;
}
if (prg->devtype->has_dprc_fixup && modifier) {
if (modifier) {
x_offset %= mt_w;
y_offset %= mt_h;
@ -187,7 +174,7 @@ void prg_configure(struct prg *prg, unsigned int width, unsigned int height,
* address TKT339017:
* fixup for burst size vs stride mismatch
*/
if (prg->devtype->has_dprc_fixup && modifier)
if (modifier)
stride = round_up(stride + round_up(_baddr % 8, 8), burst_size);
else
stride = round_up(stride, burst_size);
@ -199,7 +186,7 @@ void prg_configure(struct prg *prg, unsigned int width, unsigned int height,
*/
if (prg->is_auxiliary && stride <= burst_size) {
height /= 2;
if (prg->devtype->has_dprc_fixup && modifier)
if (modifier)
y_offset /= 2;
}
@ -307,7 +294,7 @@ bool prg_stride_double_check(struct prg *prg,
return false;
}
if (prg->devtype->has_dprc_fixup && modifier) {
if (modifier) {
x_offset %= mt_w;
/* consider x offset to calculate stride */
@ -328,7 +315,7 @@ bool prg_stride_double_check(struct prg *prg,
* address TKT339017:
* fixup for burst size vs stride mismatch
*/
if (prg->devtype->has_dprc_fixup && modifier)
if (modifier)
stride = round_up(stride + round_up(_baddr % 8, 8), burst_size);
else
stride = round_up(stride, burst_size);
@ -386,15 +373,13 @@ prg_lookup_by_phandle(struct device *dev, const char *name, int index)
EXPORT_SYMBOL_GPL(prg_lookup_by_phandle);
static const struct of_device_id prg_dt_ids[] = {
{ .compatible = "fsl,imx8qm-prg", .data = &prg_type_v1, },
{ .compatible = "fsl,imx8qxp-prg", .data = &prg_type_v2, },
{ .compatible = "fsl,imx8qm-prg", },
{ .compatible = "fsl,imx8qxp-prg", },
{ /* sentinel */ },
};
static int prg_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
of_match_device(prg_dt_ids, &pdev->dev);
struct device *dev = &pdev->dev;
struct resource *res;
struct prg *prg;
@ -403,8 +388,6 @@ static int prg_probe(struct platform_device *pdev)
if (!prg)
return -ENOMEM;
prg->devtype = of_id->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
prg->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(prg->base))

2
include/video/dpu.h
View File

@ -680,8 +680,6 @@ struct dpu_fetchunit *fetchdecode_get_fetcheco(struct dpu_fetchunit *fu);
struct dpu_hscaler *fetchdecode_get_hscaler(struct dpu_fetchunit *fu);
struct dpu_vscaler *fetchdecode_get_vscaler(struct dpu_fetchunit *fu);
bool dpu_has_prefetch_fixup(struct dpu_soc *dpu);
bool dpu_vproc_has_fetcheco_cap(u32 cap_mask);
bool dpu_vproc_has_hscale_cap(u32 cap_mask);
bool dpu_vproc_has_vscale_cap(u32 cap_mask);