pinctrl: exynos: Use one IRQ domain per pin bank
Instead of registering one IRQ domain for all pin banks of a pin
controller, this patch implements registration of per-bank domains.
At a cost of a little memory overhead (~2.5KiB for all GPIO interrupts
of Exynos4x12) it simplifies driver code and device tree sources,
because GPIO interrupts can be now specified per banks.
Example:
device {
/* ... */
interrupt-parent = <&gpa1>;
interrupts = <3 0>;
/* ... */
};
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Tomasz Figa
Linus Walleij
parent
1b6056d6db
commit
595be7268a
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@ -46,16 +46,12 @@
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compatible = "samsung,pinctrl-exynos4210";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,pinctrl-exynos4210";
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakup_eint: wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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@ -40,46 +40,46 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
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static void exynos_gpio_irq_unmask(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
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struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
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unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
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unsigned long mask;
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mask = readl(d->virt_base + reg_mask);
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mask &= ~(1 << edata->pin);
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mask &= ~(1 << irqd->hwirq);
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writel(mask, d->virt_base + reg_mask);
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}
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static void exynos_gpio_irq_mask(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
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struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
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unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
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unsigned long mask;
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mask = readl(d->virt_base + reg_mask);
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mask |= 1 << edata->pin;
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mask |= 1 << irqd->hwirq;
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writel(mask, d->virt_base + reg_mask);
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}
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static void exynos_gpio_irq_ack(struct irq_data *irqd)
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{
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struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
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struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
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unsigned long reg_pend = d->ctrl->geint_pend + edata->eint_offset;
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset;
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writel(1 << edata->pin, d->virt_base + reg_pend);
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writel(1 << irqd->hwirq, d->virt_base + reg_pend);
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}
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static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
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struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
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struct samsung_pinctrl_drv_data *d = bank->drvdata;
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struct samsung_pin_ctrl *ctrl = d->ctrl;
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struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
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struct samsung_pin_bank *bank = edata->bank;
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unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
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unsigned int pin = irqd->hwirq;
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unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
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unsigned int con, trig_type;
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unsigned long reg_con = ctrl->geint_con + edata->eint_offset;
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unsigned long reg_con = ctrl->geint_con + bank->eint_offset;
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unsigned int mask;
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switch (type) {
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@ -114,7 +114,7 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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writel(con, d->virt_base + reg_con);
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reg_con = bank->pctl_offset;
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shift = edata->pin * bank->func_width;
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shift = pin * bank->func_width;
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mask = (1 << bank->func_width) - 1;
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con = readl(d->virt_base + reg_con);
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@ -136,81 +136,23 @@ static struct irq_chip exynos_gpio_irq_chip = {
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.irq_set_type = exynos_gpio_irq_set_type,
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};
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/*
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* given a controller-local external gpio interrupt number, prepare the handler
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* data for it.
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*/
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static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
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struct samsung_pinctrl_drv_data *d)
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{
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struct samsung_pin_bank *bank = d->ctrl->pin_banks;
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struct exynos_geint_data *eint_data;
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unsigned int nr_banks = d->ctrl->nr_banks, idx;
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unsigned int irq_base = 0;
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if (hw >= d->ctrl->nr_gint) {
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dev_err(d->dev, "unsupported ext-gpio interrupt\n");
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return NULL;
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}
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for (idx = 0; idx < nr_banks; idx++, bank++) {
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if (bank->eint_type != EINT_TYPE_GPIO)
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continue;
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if ((hw >= irq_base) && (hw < (irq_base + bank->nr_pins)))
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break;
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irq_base += bank->nr_pins;
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}
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if (idx == nr_banks) {
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dev_err(d->dev, "pin bank not found for ext-gpio interrupt\n");
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return NULL;
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}
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eint_data = devm_kzalloc(d->dev, sizeof(*eint_data), GFP_KERNEL);
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if (!eint_data) {
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dev_err(d->dev, "no memory for eint-gpio data\n");
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return NULL;
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}
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eint_data->bank = bank;
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eint_data->pin = hw - irq_base;
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eint_data->eint_offset = bank->eint_offset;
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return eint_data;
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}
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static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct samsung_pinctrl_drv_data *d = h->host_data;
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struct exynos_geint_data *eint_data;
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struct samsung_pin_bank *b = h->host_data;
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eint_data = exynos_get_eint_data(hw, d);
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if (!eint_data)
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return -EINVAL;
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irq_set_handler_data(virq, eint_data);
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_data(virq, b);
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irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
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handle_level_irq);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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static void exynos_gpio_irq_unmap(struct irq_domain *h, unsigned int virq)
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{
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struct samsung_pinctrl_drv_data *d = h->host_data;
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struct exynos_geint_data *eint_data;
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eint_data = irq_get_handler_data(virq);
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devm_kfree(d->dev, eint_data);
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}
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/*
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* irq domain callbacks for external gpio interrupt controller.
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*/
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static const struct irq_domain_ops exynos_gpio_irqd_ops = {
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.map = exynos_gpio_irq_map,
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.unmap = exynos_gpio_irq_unmap,
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.xlate = irq_domain_xlate_twocell,
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};
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@ -229,7 +171,7 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
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return IRQ_HANDLED;
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bank += (group - 1);
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virq = irq_linear_revmap(d->gpio_irqd, bank->irq_base + pin);
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virq = irq_linear_revmap(bank->irq_domain, pin);
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if (!virq)
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return IRQ_NONE;
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generic_handle_irq(virq);
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@ -242,8 +184,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
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*/
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static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
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{
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struct samsung_pin_bank *bank;
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struct device *dev = d->dev;
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unsigned int ret;
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unsigned int i;
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if (!d->irq) {
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dev_err(dev, "irq number not available\n");
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@ -257,11 +201,16 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
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return -ENXIO;
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}
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d->gpio_irqd = irq_domain_add_linear(dev->of_node, d->ctrl->nr_gint,
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&exynos_gpio_irqd_ops, d);
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if (!d->gpio_irqd) {
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dev_err(dev, "gpio irq domain allocation failed\n");
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return -ENXIO;
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bank = d->ctrl->pin_banks;
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for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
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if (bank->eint_type != EINT_TYPE_GPIO)
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continue;
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bank->irq_domain = irq_domain_add_linear(bank->of_node,
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bank->nr_pins, &exynos_gpio_irqd_ops, bank);
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if (!bank->irq_domain) {
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dev_err(dev, "gpio irq domain add failed\n");
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return -ENXIO;
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}
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}
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return 0;
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@ -73,18 +73,6 @@
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.name = id \
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}
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/**
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* struct exynos_geint_data: gpio eint specific data for irq_chip callbacks.
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* @bank: pin bank from which this gpio interrupt originates.
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* @pin: pin number within the bank.
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* @eint_offset: offset to be added to the con/pend/mask register bank base.
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*/
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struct exynos_geint_data {
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struct samsung_pin_bank *bank;
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u32 pin;
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u32 eint_offset;
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};
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/**
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
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* generated by the external wakeup interrupt controller.
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@ -813,10 +813,6 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
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bank->drvdata = d;
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bank->pin_base = ctrl->nr_pins;
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ctrl->nr_pins += bank->nr_pins;
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if (bank->eint_type == EINT_TYPE_GPIO) {
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bank->irq_base = ctrl->nr_gint;
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ctrl->nr_gint += bank->nr_pins;
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}
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}
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for_each_child_of_node(node, np) {
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@ -109,10 +109,10 @@ struct samsung_pinctrl_drv_data;
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* @conpdn_width: width of the sleep mode function selector bin field.
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* @pudpdn_width: width of the sleep mode pull up/down selector bit field.
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* @eint_type: type of the external interrupt supported by the bank.
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* @irq_base: starting controller local irq number of the bank.
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* @name: name to be prefixed for each pin in this pin bank.
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* @of_node: OF node of the bank.
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* @drvdata: link to controller driver data
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* @irq_domain: IRQ domain of the bank.
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*/
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struct samsung_pin_bank {
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u32 pctl_offset;
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@ -125,10 +125,10 @@ struct samsung_pin_bank {
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u8 pudpdn_width;
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enum eint_type eint_type;
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u32 eint_offset;
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u32 irq_base;
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char *name;
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struct device_node *of_node;
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struct samsung_pinctrl_drv_data *drvdata;
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struct irq_domain *irq_domain;
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};
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/**
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@ -137,7 +137,6 @@ struct samsung_pin_bank {
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* @nr_banks: number of pin banks.
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* @base: starting system wide pin number.
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* @nr_pins: number of pins supported by the controller.
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* @nr_gint: number of external gpio interrupts supported.
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* @nr_wint: number of external wakeup interrupts supported.
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* @geint_con: offset of the ext-gpio controller registers.
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* @geint_mask: offset of the ext-gpio interrupt mask registers.
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@ -158,7 +157,6 @@ struct samsung_pin_ctrl {
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u32 base;
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u32 nr_pins;
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u32 nr_gint;
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u32 nr_wint;
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u32 geint_con;
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@ -205,7 +203,6 @@ struct samsung_pinctrl_drv_data {
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const struct samsung_pmx_func *pmx_functions;
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unsigned int nr_functions;
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struct irq_domain *gpio_irqd;
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struct irq_domain *wkup_irqd;
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struct gpio_chip *gc;
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