dmaengine: omap-dma: move register read/writes into omap-dma.c
Export the DMA register information from the SoC specific data, such that we can access the registers directly in omap-dma.c, mapping the register region ourselves as well. Rather than calculating the DMA channel register in its entirety for each access, we pre-calculate an offset base address for the allocated DMA channel and then just use the appropriate register offset. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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34a378fcb9
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@ -261,9 +261,13 @@ static const struct platform_device_info omap_dma_dev_info = {
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.name = "omap-dma-engine",
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.id = -1,
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.dma_mask = DMA_BIT_MASK(32),
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.res = res,
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.num_res = 1,
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};
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static struct omap_system_dma_plat_info dma_plat_info __initdata = {
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.reg_map = reg_map,
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.channel_stride = 0x40,
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.show_dma_caps = omap1_show_dma_caps,
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.clear_lch_regs = omap1_clear_lch_regs,
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.clear_dma = omap1_clear_dma,
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@ -205,12 +205,20 @@ static unsigned configure_dma_errata(void)
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}
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static struct omap_system_dma_plat_info dma_plat_info __initdata = {
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.reg_map = reg_map,
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.channel_stride = 0x60,
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.show_dma_caps = omap2_show_dma_caps,
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.clear_dma = omap2_clear_dma,
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.dma_write = dma_write,
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.dma_read = dma_read,
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};
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static struct platform_device_info omap_dma_dev_info = {
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.name = "omap-dma-engine",
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.id = -1,
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.dma_mask = DMA_BIT_MASK(32),
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};
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/* One time initializations */
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static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
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{
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@ -231,11 +239,15 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
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return PTR_ERR(pdev);
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}
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omap_dma_dev_info.res = pdev->resource;
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omap_dma_dev_info.num_res = pdev->num_resources;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
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return -EINVAL;
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}
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dma_base = ioremap(mem->start, resource_size(mem));
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if (!dma_base) {
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dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
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@ -256,12 +268,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
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return 0;
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}
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static const struct platform_device_info omap_dma_dev_info = {
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.name = "omap-dma-engine",
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.id = -1,
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.dma_mask = DMA_BIT_MASK(32),
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};
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static int __init omap2_system_dma_init(void)
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{
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struct platform_device *pdev;
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@ -27,13 +27,16 @@ struct omap_dmadev {
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spinlock_t lock;
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struct tasklet_struct task;
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struct list_head pending;
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void __iomem *base;
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const struct omap_dma_reg *reg_map;
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struct omap_system_dma_plat_info *plat;
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};
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struct omap_chan {
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struct virt_dma_chan vc;
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struct list_head node;
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struct omap_system_dma_plat_info *plat;
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void __iomem *channel_base;
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const struct omap_dma_reg *reg_map;
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struct dma_slave_config cfg;
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unsigned dma_sig;
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@ -170,24 +173,77 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
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kfree(container_of(vd, struct omap_desc, vd));
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}
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static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
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{
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switch (type) {
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case OMAP_DMA_REG_16BIT:
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writew_relaxed(val, addr);
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break;
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case OMAP_DMA_REG_2X16BIT:
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writew_relaxed(val, addr);
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writew_relaxed(val >> 16, addr + 2);
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break;
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case OMAP_DMA_REG_32BIT:
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writel_relaxed(val, addr);
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break;
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default:
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WARN_ON(1);
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}
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}
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static unsigned omap_dma_read(unsigned type, void __iomem *addr)
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{
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unsigned val;
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switch (type) {
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case OMAP_DMA_REG_16BIT:
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val = readw_relaxed(addr);
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break;
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case OMAP_DMA_REG_2X16BIT:
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val = readw_relaxed(addr);
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val |= readw_relaxed(addr + 2) << 16;
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break;
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case OMAP_DMA_REG_32BIT:
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val = readl_relaxed(addr);
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break;
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default:
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WARN_ON(1);
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val = 0;
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}
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return val;
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}
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static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
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{
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od->plat->dma_write(val, reg, 0);
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const struct omap_dma_reg *r = od->reg_map + reg;
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WARN_ON(r->stride);
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omap_dma_write(val, r->type, od->base + r->offset);
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}
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static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
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{
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return od->plat->dma_read(reg, 0);
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const struct omap_dma_reg *r = od->reg_map + reg;
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WARN_ON(r->stride);
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return omap_dma_read(r->type, od->base + r->offset);
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}
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static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
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{
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c->plat->dma_write(val, reg, c->dma_ch);
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const struct omap_dma_reg *r = c->reg_map + reg;
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omap_dma_write(val, r->type, c->channel_base + r->offset);
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}
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static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
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{
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return c->plat->dma_read(reg, c->dma_ch);
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const struct omap_dma_reg *r = c->reg_map + reg;
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return omap_dma_read(r->type, c->channel_base + r->offset);
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}
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static void omap_dma_clear_csr(struct omap_chan *c)
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@ -198,6 +254,12 @@ static void omap_dma_clear_csr(struct omap_chan *c)
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omap_dma_chan_write(c, CSR, ~0);
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}
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static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
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unsigned lch)
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{
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c->channel_base = od->base + od->plat->channel_stride * lch;
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}
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static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
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{
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struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
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@ -400,18 +462,26 @@ static void omap_dma_sched(unsigned long data)
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static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct omap_dmadev *od = to_omap_dma_dev(chan->device);
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struct omap_chan *c = to_omap_dma_chan(chan);
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int ret;
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dev_dbg(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);
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dev_dbg(od->ddev.dev, "allocating channel for %u\n", c->dma_sig);
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return omap_request_dma(c->dma_sig, "DMA engine",
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omap_dma_callback, c, &c->dma_ch);
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ret = omap_request_dma(c->dma_sig, "DMA engine", omap_dma_callback,
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c, &c->dma_ch);
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if (ret >= 0)
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omap_dma_assign(od, c, c->dma_ch);
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return ret;
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}
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static void omap_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct omap_chan *c = to_omap_dma_chan(chan);
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c->channel_base = NULL;
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vchan_free_chan_resources(&c->vc);
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omap_free_dma(c->dma_ch);
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@ -917,7 +987,7 @@ static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
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if (!c)
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return -ENOMEM;
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c->plat = od->plat;
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c->reg_map = od->reg_map;
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c->dma_sig = dma_sig;
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c->vc.desc_free = omap_dma_desc_free;
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vchan_init(&c->vc, &od->ddev);
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@ -944,16 +1014,24 @@ static void omap_dma_free(struct omap_dmadev *od)
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static int omap_dma_probe(struct platform_device *pdev)
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{
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struct omap_dmadev *od;
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struct resource *res;
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int rc, i;
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od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
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if (!od)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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od->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(od->base))
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return PTR_ERR(od->base);
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od->plat = omap_get_plat_info();
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if (!od->plat)
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return -EPROBE_DEFER;
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od->reg_map = od->plat->reg_map;
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dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
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dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
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od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
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@ -285,6 +285,8 @@ struct omap_dma_reg {
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/* System DMA platform data structure */
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struct omap_system_dma_plat_info {
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const struct omap_dma_reg *reg_map;
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unsigned channel_stride;
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struct omap_dma_dev_attr *dma_attr;
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u32 errata;
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void (*show_dma_caps)(void);
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