ARM: dts: watchdog0 cannot reliably trigger reset
On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger a reset to the CPU. The workaround would be to use watchdog1 instead. Also for watchdog1, there is a dependency on the bootloader to enable the boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the control register in the clock manager module of Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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@ -160,6 +160,6 @@
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status = "okay";
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status = "okay";
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};
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};
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&watchdog0 {
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&watchdog1 {
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status = "okay";
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status = "okay";
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};
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};
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