mtd: omap: add support for nand prefetch-read and post-write
This patch adds prefetch support to access nand flash in mpu mode. This patch also adds 8-bit nand support (omap_read/write_buf8). Prefetch can be used for both 8- and 16-bit devices. Signed-off-by: Vimal Singh <vimalsingh@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -57,6 +57,11 @@
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#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
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#define GPMC_SECTION_SHIFT 28 /* 128 MB */
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#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
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#define CS_NUM_SHIFT 24
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#define ENABLE_PREFETCH (0x1 << 7)
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#define DMA_MPU_MODE 2
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static struct resource gpmc_mem_root;
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static struct resource gpmc_cs_mem[GPMC_CS_NUM];
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static DEFINE_SPINLOCK(gpmc_mem_lock);
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@ -386,6 +391,63 @@ void gpmc_cs_free(int cs)
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}
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EXPORT_SYMBOL(gpmc_cs_free);
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/**
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* gpmc_prefetch_enable - configures and starts prefetch transfer
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* @cs: nand cs (chip select) number
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* @dma_mode: dma mode enable (1) or disable (0)
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* @u32_count: number of bytes to be transferred
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* @is_write: prefetch read(0) or write post(1) mode
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*/
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int gpmc_prefetch_enable(int cs, int dma_mode,
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unsigned int u32_count, int is_write)
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{
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uint32_t prefetch_config1;
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if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
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/* Set the amount of bytes to be prefetched */
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gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
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/* Set dma/mpu mode, the prefetch read / post write and
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* enable the engine. Set which cs is has requested for.
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*/
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prefetch_config1 = ((cs << CS_NUM_SHIFT) |
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PREFETCH_FIFOTHRESHOLD |
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ENABLE_PREFETCH |
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(dma_mode << DMA_MPU_MODE) |
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(0x1 & is_write));
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gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
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} else {
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return -EBUSY;
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}
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/* Start the prefetch engine */
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gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
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return 0;
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}
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EXPORT_SYMBOL(gpmc_prefetch_enable);
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/**
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* gpmc_prefetch_reset - disables and stops the prefetch engine
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*/
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void gpmc_prefetch_reset(void)
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{
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/* Stop the PFPW engine */
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gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
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/* Reset/disable the PFPW engine */
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gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
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}
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EXPORT_SYMBOL(gpmc_prefetch_reset);
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/**
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* gpmc_prefetch_status - reads prefetch status of engine
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*/
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int gpmc_prefetch_status(void)
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{
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return gpmc_read_reg(GPMC_PREFETCH_STATUS);
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}
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EXPORT_SYMBOL(gpmc_prefetch_status);
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static void __init gpmc_mem_init(void)
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{
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int cs;
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@ -452,6 +514,5 @@ void __init gpmc_init(void)
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l &= 0x03 << 3;
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l |= (0x02 << 3) | (1 << 0);
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gpmc_write_reg(GPMC_SYSCONFIG, l);
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gpmc_mem_init();
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}
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@ -103,6 +103,10 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
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extern void gpmc_cs_free(int cs);
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extern int gpmc_cs_set_reserved(int cs, int reserved);
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extern int gpmc_cs_reserved(int cs);
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extern int gpmc_prefetch_enable(int cs, int dma_mode,
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unsigned int u32_count, int is_write);
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extern void gpmc_prefetch_reset(void);
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extern int gpmc_prefetch_status(void);
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extern void __init gpmc_init(void);
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#endif
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@ -80,6 +80,14 @@ config MTD_NAND_OMAP2
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help
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Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms.
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config MTD_NAND_OMAP_PREFETCH
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bool "GPMC prefetch support for NAND Flash device"
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depends on MTD_NAND && MTD_NAND_OMAP2
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default y
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help
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The NAND device can be accessed for Read/Write using GPMC PREFETCH engine
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to improve the performance.
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config MTD_NAND_TS7250
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tristate "NAND Flash device on TS-7250 board"
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depends on MACH_TS72XX
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@ -112,6 +112,16 @@
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static const char *part_probes[] = { "cmdlinepart", NULL };
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#endif
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#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH
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static int use_prefetch = 1;
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/* "modprobe ... use_prefetch=0" etc */
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module_param(use_prefetch, bool, 0);
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MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH");
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#else
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const int use_prefetch;
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#endif
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struct omap_nand_info {
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struct nand_hw_control controller;
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struct omap_nand_platform_data *pdata;
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@ -124,6 +134,7 @@ struct omap_nand_info {
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unsigned long phys_base;
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void __iomem *gpmc_cs_baseaddr;
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void __iomem *gpmc_baseaddr;
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void __iomem *nand_pref_fifo_add;
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};
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/**
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@ -188,6 +199,38 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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__raw_writeb(cmd, info->nand.IO_ADDR_W);
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}
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/**
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* omap_read_buf8 - read data from NAND controller into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *nand = mtd->priv;
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ioread8_rep(nand->IO_ADDR_R, buf, len);
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}
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/**
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* omap_write_buf8 - write buffer to NAND controller
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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u_char *p = (u_char *)buf;
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while (len--) {
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iowrite8(*p++, info->nand.IO_ADDR_W);
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while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
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GPMC_STATUS) & GPMC_BUF_FULL));
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}
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}
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/**
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* omap_read_buf16 - read data from NAND controller into buffer
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* @mtd: MTD device structure
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@ -198,7 +241,7 @@ static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *nand = mtd->priv;
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__raw_readsw(nand->IO_ADDR_R, buf, len / 2);
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ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
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}
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/**
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@ -217,13 +260,101 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
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len >>= 1;
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while (len--) {
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writew(*p++, info->nand.IO_ADDR_W);
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iowrite16(*p++, info->nand.IO_ADDR_W);
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while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
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GPMC_STATUS) & GPMC_BUF_FULL))
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;
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}
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}
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/**
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* omap_read_buf_pref - read data from NAND controller into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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uint32_t pfpw_status = 0, r_count = 0;
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int ret = 0;
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u32 *p = (u32 *)buf;
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/* take care of subpage reads */
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for (; len % 4 != 0; ) {
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*buf++ = __raw_readb(info->nand.IO_ADDR_R);
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len--;
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}
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p = (u32 *) buf;
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0);
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if (ret) {
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/* PFPW engine is busy, use cpu copy method */
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if (info->nand.options & NAND_BUSWIDTH_16)
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omap_read_buf16(mtd, buf, len);
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else
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omap_read_buf8(mtd, buf, len);
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} else {
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do {
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pfpw_status = gpmc_prefetch_status();
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r_count = ((pfpw_status >> 24) & 0x7F) >> 2;
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ioread32_rep(info->nand_pref_fifo_add, p, r_count);
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p += r_count;
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len -= r_count << 2;
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} while (len);
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset();
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}
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}
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/**
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* omap_write_buf_pref - write buffer to NAND controller
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void omap_write_buf_pref(struct mtd_info *mtd,
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const u_char *buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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uint32_t pfpw_status = 0, w_count = 0;
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int i = 0, ret = 0;
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u16 *p = (u16 *) buf;
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/* take care of subpage writes */
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if (len % 2 != 0) {
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writeb(*buf, info->nand.IO_ADDR_R);
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p = (u16 *)(buf + 1);
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len--;
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}
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1);
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if (ret) {
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/* PFPW engine is busy, use cpu copy method */
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if (info->nand.options & NAND_BUSWIDTH_16)
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omap_write_buf16(mtd, buf, len);
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else
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omap_write_buf8(mtd, buf, len);
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} else {
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pfpw_status = gpmc_prefetch_status();
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while (pfpw_status & 0x3FFF) {
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w_count = ((pfpw_status >> 24) & 0x7F) >> 1;
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for (i = 0; (i < w_count) && len; i++, len -= 2)
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iowrite16(*p++, info->nand_pref_fifo_add);
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pfpw_status = gpmc_prefetch_status();
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}
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset();
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}
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}
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/**
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* omap_verify_buf - Verify chip data against buffer
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* @mtd: MTD device structure
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@ -658,17 +789,12 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
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err = -ENOMEM;
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goto out_release_mem_region;
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}
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info->nand.controller = &info->controller;
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info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
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info->nand.cmd_ctrl = omap_hwcontrol;
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/* REVISIT: only supports 16-bit NAND flash */
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info->nand.read_buf = omap_read_buf16;
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info->nand.write_buf = omap_write_buf16;
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info->nand.verify_buf = omap_verify_buf;
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/*
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* If RDY/BSY line is connected to OMAP then use the omap ready
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* funcrtion and the generic nand_wait function which reads the status
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@ -689,6 +815,23 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
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== 0x1000)
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info->nand.options |= NAND_BUSWIDTH_16;
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if (use_prefetch) {
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/* copy the virtual address of nand base for fifo access */
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info->nand_pref_fifo_add = info->nand.IO_ADDR_R;
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info->nand.read_buf = omap_read_buf_pref;
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info->nand.write_buf = omap_write_buf_pref;
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} else {
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if (info->nand.options & NAND_BUSWIDTH_16) {
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info->nand.read_buf = omap_read_buf16;
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info->nand.write_buf = omap_write_buf16;
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} else {
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info->nand.read_buf = omap_read_buf8;
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info->nand.write_buf = omap_write_buf8;
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}
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}
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info->nand.verify_buf = omap_verify_buf;
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#ifdef CONFIG_MTD_NAND_OMAP_HWECC
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info->nand.ecc.bytes = 3;
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info->nand.ecc.size = 512;
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platform_set_drvdata(pdev, NULL);
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/* Release NAND device, its internal structures and partitions */
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nand_release(&info->mtd);
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iounmap(info->nand.IO_ADDR_R);
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iounmap(info->nand_pref_fifo_add);
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kfree(&info->mtd);
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return 0;
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}
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