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MLK-12262-3 ARM: imx: reduce DDR3 normal frequency to 400MHz for i.MX7D TO1.1 

i.MX7D TO1.1 only supports DDR3 running at max frequency of 400MHz,
update busfreq driver accordingly.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
pull/10/head
Anson Huang 2016-01-26 15:37:15 +08:00 committed by Jason Liu
parent 6a2fbff6f8
commit 5a03f84782
2 changed files with 12 additions and 5 deletions
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11
arch/arm/mach-imx/busfreq-imx.c
View File

@ -1275,9 +1275,16 @@ static int busfreq_probe(struct platform_device *pdev)
TT_ATTRIB_NON_CACHEABLE_1M;
}
if (cpu_is_imx7d())
if (cpu_is_imx7d()) {
ddr_type = imx_ddrc_get_ddr_type();
/* reduce ddr3 normal rate to 400M due to CKE issue on TO1.1 */
if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_1 &&
ddr_type == IMX_DDR_TYPE_DDR3) {
ddr_normal_rate = 400000000;
pr_info("ddr3 normal rate changed to 400MHz for TO1.1.\n");
}
err = init_ddrc_ddr_settings(pdev);
else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
} else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
cpu_is_imx6sll()) {
ddr_type = imx_mmdc_get_ddr_type();
if (ddr_type == IMX_DDR_TYPE_DDR3)

6
arch/arm/mach-imx/ddr3_freq_imx7d.S
View File

@ -326,12 +326,12 @@
cmp r7, #0x11
bne 22f
ldr r7, =0x1d1d1d1d
ldr r7, =0x40404040
str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0]
ldr r7, =0x10101010
ldr r7, =0x18181818
str r7, [r5, #DDRPHY_CA_DSKEW_CON0]
str r7, [r5, #DDRPHY_CA_DSKEW_CON1]
ldr r7, =0x1d1d1010
ldr r7, =0x40401818
str r7, [r5, #DDRPHY_CA_DSKEW_CON2]
b 23f
22: