MLK-12262-3 ARM: imx: reduce DDR3 normal frequency to 400MHz for i.MX7D TO1.1
i.MX7D TO1.1 only supports DDR3 running at max frequency of 400MHz, update busfreq driver accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>pull/10/head
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6a2fbff6f8
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5a03f84782
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@ -1275,9 +1275,16 @@ static int busfreq_probe(struct platform_device *pdev)
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TT_ATTRIB_NON_CACHEABLE_1M;
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}
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if (cpu_is_imx7d())
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if (cpu_is_imx7d()) {
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ddr_type = imx_ddrc_get_ddr_type();
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/* reduce ddr3 normal rate to 400M due to CKE issue on TO1.1 */
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if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_1 &&
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ddr_type == IMX_DDR_TYPE_DDR3) {
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ddr_normal_rate = 400000000;
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pr_info("ddr3 normal rate changed to 400MHz for TO1.1.\n");
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}
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err = init_ddrc_ddr_settings(pdev);
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else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
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} else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() ||
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cpu_is_imx6sll()) {
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ddr_type = imx_mmdc_get_ddr_type();
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if (ddr_type == IMX_DDR_TYPE_DDR3)
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@ -326,12 +326,12 @@
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cmp r7, #0x11
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bne 22f
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ldr r7, =0x1d1d1d1d
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ldr r7, =0x40404040
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str r7, [r5, #DDRPHY_CA_WLDSKEW_CON0]
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ldr r7, =0x10101010
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ldr r7, =0x18181818
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str r7, [r5, #DDRPHY_CA_DSKEW_CON0]
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str r7, [r5, #DDRPHY_CA_DSKEW_CON1]
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ldr r7, =0x1d1d1010
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ldr r7, =0x40401818
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str r7, [r5, #DDRPHY_CA_DSKEW_CON2]
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b 23f
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22:
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