perf/x86/intel: Enable C-state residency events for Apollo Lake
Goldmont microarchitecture supports C1/C3/C6, PC2/PC3/PC6/PC10 state residency counters, the patch enables them for Apollo Lake platform. The MSR information is based on Intel Software Developers' Manual, Vol. 4, Order No. 335592, Table 2-6 and 2-12. Signed-off-by: Harry Pan <harry.pan@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: bp@suse.de Cc: davidcc@google.com Cc: gs0622@gmail.com Cc: lukasz.odzioba@intel.com Cc: piotr.luc@intel.com Cc: srinivas.pandruvada@linux.intel.com Link: http://lkml.kernel.org/r/20170717103749.24337-1-harry.pan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -40,16 +40,16 @@
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* Model specific counters:
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* MSR_CORE_C1_RES: CORE C1 Residency Counter
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* perf code: 0x00
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* Available model: SLM,AMT
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* Available model: SLM,AMT,GLM
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* Scope: Core (each processor core has a MSR)
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* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
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* perf code: 0x01
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* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
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* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
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* Scope: Core
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* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
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* perf code: 0x02
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* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
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* SKL,KNL
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* SKL,KNL,GLM
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* Scope: Core
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* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
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* perf code: 0x03
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@ -57,16 +57,17 @@
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* Scope: Core
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* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
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* perf code: 0x00
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* Available model: SNB,IVB,HSW,BDW,SKL,KNL
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* Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
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* Scope: Package (physical package)
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* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
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* perf code: 0x01
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* Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
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* GLM
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* Scope: Package (physical package)
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* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
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* perf code: 0x02
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* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
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* SKL,KNL
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* SKL,KNL,GLM
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* Scope: Package (physical package)
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* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
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* perf code: 0x03
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@ -82,7 +83,7 @@
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* Scope: Package (physical package)
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* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
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* perf code: 0x06
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* Available model: HSW ULT only
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* Available model: HSW ULT, GLM
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* Scope: Package (physical package)
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*
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*/
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@ -504,6 +505,17 @@ static const struct cstate_model knl_cstates __initconst = {
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};
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static const struct cstate_model glm_cstates __initconst = {
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.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
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BIT(PERF_CSTATE_CORE_C3_RES) |
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BIT(PERF_CSTATE_CORE_C6_RES),
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.pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
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BIT(PERF_CSTATE_PKG_C3_RES) |
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BIT(PERF_CSTATE_PKG_C6_RES) |
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BIT(PERF_CSTATE_PKG_C10_RES),
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};
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#define X86_CSTATES_MODEL(model, states) \
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{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) }
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@ -546,6 +558,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
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X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
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X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
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{ },
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};
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MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
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