Merge branches 'sh/core', 'sh/io-overhaul' and 'sh/urgent' into sh-latest
This commit is contained in:
Paul Mundt
commit
5c4986b8a9
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@ -161,7 +161,8 @@ config ARCH_HAS_CPU_IDLE_WAIT
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def_bool y
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config NO_IOPORT
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bool
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def_bool !PCI
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depends on !SH_CAYMAN && !SH_SH4202_MICRODEV
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config IO_TRAPPED
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bool
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@ -29,8 +29,6 @@ unsigned short secureedge5410_ioport;
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*/
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static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
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{
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ctrl_delay(); /* dummy read */
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printk("SnapGear: erase switch interrupt!\n");
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return IRQ_HANDLED;
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@ -382,14 +382,13 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
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struct pci_channel *chan = dev->sysdata;
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if (unlikely(!chan->io_map_base)) {
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chan->io_map_base = generic_io_base;
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chan->io_map_base = sh_io_port_base;
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if (pci_domains_supported)
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panic("To avoid data corruption io_map_base MUST be "
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"set with multiple PCI domains.");
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}
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return (void __iomem *)(chan->io_map_base + port);
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}
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@ -1,5 +1,6 @@
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#ifndef __ASM_SH_IO_H
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#define __ASM_SH_IO_H
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/*
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* Convention:
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* read{b,w,l,q}/write{b,w,l,q} are for PCI,
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@ -15,12 +16,6 @@
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* SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
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* these have the same semantics as the __raw variants, and as such, all
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* new code should be using the __raw versions.
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*
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* All ISA I/O routines are wrapped through the machine vector. If a
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* board does not provide overrides, a generic set that are copied in
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* from the default machine vector are used instead. These are largely
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* for old compat code for I/O offseting to SuperIOs, all of which are
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* better handled through the machvec ioport mapping routines these days.
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*/
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#include <linux/errno.h>
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#include <asm/cache.h>
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@ -31,39 +26,10 @@
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#include <asm-generic/iomap.h>
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#ifdef __KERNEL__
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/*
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* Depending on which platform we are running on, we need different
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* I/O functions.
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*/
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#define __IO_PREFIX generic
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#define __IO_PREFIX generic
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#include <asm/io_generic.h>
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#include <asm/io_trapped.h>
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#ifdef CONFIG_HAS_IOPORT
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#define inb(p) sh_mv.mv_inb((p))
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#define inw(p) sh_mv.mv_inw((p))
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#define inl(p) sh_mv.mv_inl((p))
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#define outb(x,p) sh_mv.mv_outb((x),(p))
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#define outw(x,p) sh_mv.mv_outw((x),(p))
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#define outl(x,p) sh_mv.mv_outl((x),(p))
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#define inb_p(p) sh_mv.mv_inb_p((p))
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#define inw_p(p) sh_mv.mv_inw_p((p))
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#define inl_p(p) sh_mv.mv_inl_p((p))
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#define outb_p(x,p) sh_mv.mv_outb_p((x),(p))
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#define outw_p(x,p) sh_mv.mv_outw_p((x),(p))
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#define outl_p(x,p) sh_mv.mv_outl_p((x),(p))
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#define insb(p,b,c) sh_mv.mv_insb((p), (b), (c))
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#define insw(p,b,c) sh_mv.mv_insw((p), (b), (c))
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#define insl(p,b,c) sh_mv.mv_insl((p), (b), (c))
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#define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c))
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#define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c))
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#define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c))
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#endif
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#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
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#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
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#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
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@ -74,15 +40,196 @@
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#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
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#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
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#define readb(a) ({ u8 r_ = __raw_readb(a); mb(); r_; })
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#define readw(a) ({ u16 r_ = __raw_readw(a); mb(); r_; })
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#define readl(a) ({ u32 r_ = __raw_readl(a); mb(); r_; })
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#define readq(a) ({ u64 r_ = __raw_readq(a); mb(); r_; })
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#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
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#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
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__raw_readw(c)); __v; })
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#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \
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__raw_readl(c)); __v; })
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#define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64) \
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__raw_readq(c)); __v; })
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#define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); })
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#define writew(v,a) ({ __raw_writew((v),(a)); mb(); })
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#define writel(v,a) ({ __raw_writel((v),(a)); mb(); })
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#define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); })
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#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
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#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
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cpu_to_le16(v),c))
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#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
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cpu_to_le32(v),c))
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#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
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cpu_to_le64(v),c))
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#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
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#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
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#define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
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#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
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#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
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#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
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#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
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#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
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#define readsb(p,d,l) __raw_readsb(p,d,l)
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#define readsw(p,d,l) __raw_readsw(p,d,l)
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#define readsl(p,d,l) __raw_readsl(p,d,l)
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#define writesb(p,d,l) __raw_writesb(p,d,l)
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#define writesw(p,d,l) __raw_writesw(p,d,l)
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#define writesl(p,d,l) __raw_writesl(p,d,l)
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#define __BUILD_UNCACHED_IO(bwlq, type) \
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static inline type read##bwlq##_uncached(unsigned long addr) \
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{ \
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type ret; \
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jump_to_uncached(); \
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ret = __raw_read##bwlq(addr); \
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back_to_cached(); \
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return ret; \
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} \
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\
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static inline void write##bwlq##_uncached(type v, unsigned long addr) \
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{ \
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jump_to_uncached(); \
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__raw_write##bwlq(v, addr); \
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back_to_cached(); \
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}
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__BUILD_UNCACHED_IO(b, u8)
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__BUILD_UNCACHED_IO(w, u16)
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__BUILD_UNCACHED_IO(l, u32)
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__BUILD_UNCACHED_IO(q, u64)
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#define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
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\
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static inline void \
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pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
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unsigned int count) \
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{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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__raw_write##bwlq(*__addr, mem); \
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__addr++; \
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} \
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} \
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\
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static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
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void *addr, unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __raw_read##bwlq(mem); \
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__addr++; \
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} \
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}
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__BUILD_MEMORY_STRING(__raw_, b, u8)
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__BUILD_MEMORY_STRING(__raw_, w, u16)
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#ifdef CONFIG_SUPERH32
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void __raw_writesl(void __iomem *addr, const void *data, int longlen);
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void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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#else
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__BUILD_MEMORY_STRING(__raw_, l, u32)
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#endif
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__BUILD_MEMORY_STRING(__raw_, q, u64)
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#ifdef CONFIG_HAS_IOPORT
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/*
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* Slowdown I/O port space accesses for antique hardware.
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*/
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#undef CONF_SLOWDOWN_IO
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/*
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* On SuperH I/O ports are memory mapped, so we access them using normal
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* load/store instructions. sh_io_port_base is the virtual address to
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* which all ports are being mapped.
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*/
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extern const unsigned long sh_io_port_base;
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static inline void __set_io_port_base(unsigned long pbase)
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{
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*(unsigned long *)&sh_io_port_base = pbase;
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barrier();
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}
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#ifdef CONFIG_GENERIC_IOMAP
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#define __ioport_map ioport_map
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#else
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extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
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#endif
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#ifdef CONF_SLOWDOWN_IO
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#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
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#else
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#define SLOW_DOWN_IO
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#endif
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#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
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\
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static inline void pfx##out##bwlq##p(type val, unsigned long port) \
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{ \
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volatile type *__addr; \
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\
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__addr = __ioport_map(port, sizeof(type)); \
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*__addr = val; \
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slow; \
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} \
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\
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static inline type pfx##in##bwlq##p(unsigned long port) \
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{ \
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||||
volatile type *__addr; \
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||||
type __val; \
|
||||
\
|
||||
__addr = __ioport_map(port, sizeof(type)); \
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||||
__val = *__addr; \
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slow; \
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||||
\
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return __val; \
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||||
}
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|
||||
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
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||||
__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
|
||||
__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
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||||
|
||||
#define BUILDIO_IOPORT(bwlq, type) \
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||||
__BUILD_IOPORT_PFX(, bwlq, type)
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||||
|
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BUILDIO_IOPORT(b, u8)
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||||
BUILDIO_IOPORT(w, u16)
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||||
BUILDIO_IOPORT(l, u32)
|
||||
BUILDIO_IOPORT(q, u64)
|
||||
|
||||
#define __BUILD_IOPORT_STRING(bwlq, type) \
|
||||
\
|
||||
static inline void outs##bwlq(unsigned long port, const void *addr, \
|
||||
unsigned int count) \
|
||||
{ \
|
||||
const volatile type *__addr = addr; \
|
||||
\
|
||||
while (count--) { \
|
||||
out##bwlq(*__addr, port); \
|
||||
__addr++; \
|
||||
} \
|
||||
} \
|
||||
\
|
||||
static inline void ins##bwlq(unsigned long port, void *addr, \
|
||||
unsigned int count) \
|
||||
{ \
|
||||
volatile type *__addr = addr; \
|
||||
\
|
||||
while (count--) { \
|
||||
*__addr = in##bwlq(port); \
|
||||
__addr++; \
|
||||
} \
|
||||
}
|
||||
|
||||
__BUILD_IOPORT_STRING(b, u8)
|
||||
__BUILD_IOPORT_STRING(w, u16)
|
||||
__BUILD_IOPORT_STRING(l, u32)
|
||||
__BUILD_IOPORT_STRING(q, u64)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Legacy SuperH on-chip I/O functions
|
||||
|
|
@ -130,139 +277,11 @@ static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
|
|||
__raw_writeq(v, addr);
|
||||
}
|
||||
|
||||
extern unsigned long generic_io_base;
|
||||
|
||||
static inline void ctrl_delay(void)
|
||||
{
|
||||
__raw_readw(generic_io_base);
|
||||
}
|
||||
|
||||
#define __BUILD_UNCACHED_IO(bwlq, type) \
|
||||
static inline type read##bwlq##_uncached(unsigned long addr) \
|
||||
{ \
|
||||
type ret; \
|
||||
jump_to_uncached(); \
|
||||
ret = __raw_read##bwlq(addr); \
|
||||
back_to_cached(); \
|
||||
return ret; \
|
||||
} \
|
||||
\
|
||||
static inline void write##bwlq##_uncached(type v, unsigned long addr) \
|
||||
{ \
|
||||
jump_to_uncached(); \
|
||||
__raw_write##bwlq(v, addr); \
|
||||
back_to_cached(); \
|
||||
}
|
||||
|
||||
__BUILD_UNCACHED_IO(b, u8)
|
||||
__BUILD_UNCACHED_IO(w, u16)
|
||||
__BUILD_UNCACHED_IO(l, u32)
|
||||
__BUILD_UNCACHED_IO(q, u64)
|
||||
|
||||
#define __BUILD_MEMORY_STRING(bwlq, type) \
|
||||
\
|
||||
static inline void __raw_writes##bwlq(volatile void __iomem *mem, \
|
||||
const void *addr, unsigned int count) \
|
||||
{ \
|
||||
const volatile type *__addr = addr; \
|
||||
\
|
||||
while (count--) { \
|
||||
__raw_write##bwlq(*__addr, mem); \
|
||||
__addr++; \
|
||||
} \
|
||||
} \
|
||||
\
|
||||
static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
|
||||
void *addr, unsigned int count) \
|
||||
{ \
|
||||
volatile type *__addr = addr; \
|
||||
\
|
||||
while (count--) { \
|
||||
*__addr = __raw_read##bwlq(mem); \
|
||||
__addr++; \
|
||||
} \
|
||||
}
|
||||
|
||||
__BUILD_MEMORY_STRING(b, u8)
|
||||
__BUILD_MEMORY_STRING(w, u16)
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
void __raw_writesl(void __iomem *addr, const void *data, int longlen);
|
||||
void __raw_readsl(const void __iomem *addr, void *data, int longlen);
|
||||
#else
|
||||
__BUILD_MEMORY_STRING(l, u32)
|
||||
#endif
|
||||
|
||||
__BUILD_MEMORY_STRING(q, u64)
|
||||
|
||||
#define writesb __raw_writesb
|
||||
#define writesw __raw_writesw
|
||||
#define writesl __raw_writesl
|
||||
|
||||
#define readsb __raw_readsb
|
||||
#define readsw __raw_readsw
|
||||
#define readsl __raw_readsl
|
||||
|
||||
#define readb_relaxed(a) readb(a)
|
||||
#define readw_relaxed(a) readw(a)
|
||||
#define readl_relaxed(a) readl(a)
|
||||
#define readq_relaxed(a) readq(a)
|
||||
|
||||
#ifndef CONFIG_GENERIC_IOMAP
|
||||
/* Simple MMIO */
|
||||
#define ioread8(a) __raw_readb(a)
|
||||
#define ioread16(a) __raw_readw(a)
|
||||
#define ioread16be(a) be16_to_cpu(__raw_readw((a)))
|
||||
#define ioread32(a) __raw_readl(a)
|
||||
#define ioread32be(a) be32_to_cpu(__raw_readl((a)))
|
||||
|
||||
#define iowrite8(v,a) __raw_writeb((v),(a))
|
||||
#define iowrite16(v,a) __raw_writew((v),(a))
|
||||
#define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a))
|
||||
#define iowrite32(v,a) __raw_writel((v),(a))
|
||||
#define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a))
|
||||
|
||||
#define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c))
|
||||
#define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c))
|
||||
#define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c))
|
||||
|
||||
#define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c))
|
||||
#define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c))
|
||||
#define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c))
|
||||
#endif
|
||||
|
||||
#define mmio_insb(p,d,c) __raw_readsb(p,d,c)
|
||||
#define mmio_insw(p,d,c) __raw_readsw(p,d,c)
|
||||
#define mmio_insl(p,d,c) __raw_readsl(p,d,c)
|
||||
|
||||
#define mmio_outsb(p,s,c) __raw_writesb(p,s,c)
|
||||
#define mmio_outsw(p,s,c) __raw_writesw(p,s,c)
|
||||
#define mmio_outsl(p,s,c) __raw_writesl(p,s,c)
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
/* synco on SH-4A, otherwise a nop */
|
||||
#define mmiowb() wmb()
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT
|
||||
|
||||
/*
|
||||
* This function provides a method for the generic case where a
|
||||
* board-specific ioport_map simply needs to return the port + some
|
||||
* arbitrary port base.
|
||||
*
|
||||
* We use this at board setup time to implicitly set the port base, and
|
||||
* as a result, we can use the generic ioport_map.
|
||||
*/
|
||||
static inline void __set_io_port_base(unsigned long pbase)
|
||||
{
|
||||
generic_io_base = pbase;
|
||||
}
|
||||
|
||||
#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
|
||||
|
||||
#endif
|
||||
|
||||
/* We really want to try and get these to memcpy etc */
|
||||
void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
|
||||
void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
|
||||
|
|
@ -395,10 +414,6 @@ static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
|
|||
#define ioremap_nocache ioremap
|
||||
#define iounmap __iounmap
|
||||
|
||||
#define maybebadio(port) \
|
||||
printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
|
||||
__func__, __LINE__, (port), (u32)__builtin_return_address(0))
|
||||
|
||||
/*
|
||||
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
||||
* access
|
||||
|
|
|
|||
|
|
@ -11,31 +11,6 @@
|
|||
#error "Don't include this header without a valid system prefix"
|
||||
#endif
|
||||
|
||||
u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
|
||||
u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
|
||||
u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
|
||||
|
||||
void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
|
||||
void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
|
||||
void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
|
||||
|
||||
u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
|
||||
u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
|
||||
u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
|
||||
void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
|
||||
void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
|
||||
void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
|
||||
|
||||
void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
|
||||
void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
|
||||
void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
|
||||
void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
|
||||
void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
|
||||
void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
|
||||
|
||||
void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
|
||||
void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
|
||||
|
||||
void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
|
||||
void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
|
||||
void IO_CONCAT(__IO_PREFIX,mem_init)(void);
|
||||
|
|
|
|||
|
|
@ -23,27 +23,6 @@ struct sh_machine_vector {
|
|||
void (*mv_init_irq)(void);
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT
|
||||
u8 (*mv_inb)(unsigned long);
|
||||
u16 (*mv_inw)(unsigned long);
|
||||
u32 (*mv_inl)(unsigned long);
|
||||
void (*mv_outb)(u8, unsigned long);
|
||||
void (*mv_outw)(u16, unsigned long);
|
||||
void (*mv_outl)(u32, unsigned long);
|
||||
|
||||
u8 (*mv_inb_p)(unsigned long);
|
||||
u16 (*mv_inw_p)(unsigned long);
|
||||
u32 (*mv_inl_p)(unsigned long);
|
||||
void (*mv_outb_p)(u8, unsigned long);
|
||||
void (*mv_outw_p)(u16, unsigned long);
|
||||
void (*mv_outl_p)(u32, unsigned long);
|
||||
|
||||
void (*mv_insb)(unsigned long, void *dst, unsigned long count);
|
||||
void (*mv_insw)(unsigned long, void *dst, unsigned long count);
|
||||
void (*mv_insl)(unsigned long, void *dst, unsigned long count);
|
||||
void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
|
||||
void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
|
||||
void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
|
||||
|
||||
void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
|
||||
void (*mv_ioport_unmap)(void __iomem *);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,6 +20,11 @@ obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \
|
|||
syscalls_$(BITS).o time.o topology.o traps.o \
|
||||
traps_$(BITS).o unwinder.o
|
||||
|
||||
ifndef CONFIG_GENERIC_IOMAP
|
||||
obj-y += iomap.o
|
||||
obj-$(CONFIG_HAS_IOPORT) += ioport.o
|
||||
endif
|
||||
|
||||
obj-y += cpu/
|
||||
obj-$(CONFIG_VSYSCALL) += vsyscall/
|
||||
obj-$(CONFIG_SMP) += smp.o
|
||||
|
|
@ -39,7 +44,6 @@ obj-$(CONFIG_DUMP_CODE) += disassemble.o
|
|||
obj-$(CONFIG_HIBERNATION) += swsusp.o
|
||||
obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o
|
||||
obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_callchain.o
|
||||
obj-$(CONFIG_HAS_IOPORT) += io_generic.o
|
||||
|
||||
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
|
||||
obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
|
||||
|
|
|
|||
|
|
@ -1,180 +0,0 @@
|
|||
/*
|
||||
* arch/sh/kernel/io_generic.c
|
||||
*
|
||||
* Copyright (C) 2000 Niibe Yutaka
|
||||
* Copyright (C) 2005 - 2007 Paul Mundt
|
||||
*
|
||||
* Generic I/O routine. These can be used where a machine specific version
|
||||
* is not required.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/machvec.h>
|
||||
|
||||
#ifdef CONFIG_CPU_SH3
|
||||
/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
|
||||
* workaround. */
|
||||
/* I'm not sure SH7709 has this kind of bug */
|
||||
#define dummy_read() __raw_readb(0xba000000)
|
||||
#else
|
||||
#define dummy_read()
|
||||
#endif
|
||||
|
||||
unsigned long generic_io_base = 0;
|
||||
|
||||
u8 generic_inb(unsigned long port)
|
||||
{
|
||||
return __raw_readb(__ioport_map(port, 1));
|
||||
}
|
||||
|
||||
u16 generic_inw(unsigned long port)
|
||||
{
|
||||
return __raw_readw(__ioport_map(port, 2));
|
||||
}
|
||||
|
||||
u32 generic_inl(unsigned long port)
|
||||
{
|
||||
return __raw_readl(__ioport_map(port, 4));
|
||||
}
|
||||
|
||||
u8 generic_inb_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = generic_inb(port);
|
||||
|
||||
ctrl_delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
u16 generic_inw_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = generic_inw(port);
|
||||
|
||||
ctrl_delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
u32 generic_inl_p(unsigned long port)
|
||||
{
|
||||
unsigned long v = generic_inl(port);
|
||||
|
||||
ctrl_delay();
|
||||
return v;
|
||||
}
|
||||
|
||||
/*
|
||||
* insb/w/l all read a series of bytes/words/longs from a fixed port
|
||||
* address. However as the port address doesn't change we only need to
|
||||
* convert the port address to real address once.
|
||||
*/
|
||||
|
||||
void generic_insb(unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
__raw_readsb(__ioport_map(port, 1), dst, count);
|
||||
dummy_read();
|
||||
}
|
||||
|
||||
void generic_insw(unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
__raw_readsw(__ioport_map(port, 2), dst, count);
|
||||
dummy_read();
|
||||
}
|
||||
|
||||
void generic_insl(unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
__raw_readsl(__ioport_map(port, 4), dst, count);
|
||||
dummy_read();
|
||||
}
|
||||
|
||||
void generic_outb(u8 b, unsigned long port)
|
||||
{
|
||||
__raw_writeb(b, __ioport_map(port, 1));
|
||||
}
|
||||
|
||||
void generic_outw(u16 b, unsigned long port)
|
||||
{
|
||||
__raw_writew(b, __ioport_map(port, 2));
|
||||
}
|
||||
|
||||
void generic_outl(u32 b, unsigned long port)
|
||||
{
|
||||
__raw_writel(b, __ioport_map(port, 4));
|
||||
}
|
||||
|
||||
void generic_outb_p(u8 b, unsigned long port)
|
||||
{
|
||||
generic_outb(b, port);
|
||||
ctrl_delay();
|
||||
}
|
||||
|
||||
void generic_outw_p(u16 b, unsigned long port)
|
||||
{
|
||||
generic_outw(b, port);
|
||||
ctrl_delay();
|
||||
}
|
||||
|
||||
void generic_outl_p(u32 b, unsigned long port)
|
||||
{
|
||||
generic_outl(b, port);
|
||||
ctrl_delay();
|
||||
}
|
||||
|
||||
/*
|
||||
* outsb/w/l all write a series of bytes/words/longs to a fixed port
|
||||
* address. However as the port address doesn't change we only need to
|
||||
* convert the port address to real address once.
|
||||
*/
|
||||
void generic_outsb(unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
__raw_writesb(__ioport_map(port, 1), src, count);
|
||||
dummy_read();
|
||||
}
|
||||
|
||||
void generic_outsw(unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
__raw_writesw(__ioport_map(port, 2), src, count);
|
||||
dummy_read();
|
||||
}
|
||||
|
||||
void generic_outsl(unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
__raw_writesl(__ioport_map(port, 4), src, count);
|
||||
dummy_read();
|
||||
}
|
||||
|
||||
void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
|
||||
{
|
||||
#ifdef P1SEG
|
||||
if (PXSEG(addr) >= P1SEG)
|
||||
return (void __iomem *)addr;
|
||||
#endif
|
||||
|
||||
return (void __iomem *)(addr + generic_io_base);
|
||||
}
|
||||
|
||||
void generic_ioport_unmap(void __iomem *addr)
|
||||
{
|
||||
}
|
||||
|
||||
#ifndef CONFIG_GENERIC_IOMAP
|
||||
void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
||||
{
|
||||
void __iomem *ret;
|
||||
|
||||
ret = __ioport_map_trapped(port, nr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return __ioport_map(port, nr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_map);
|
||||
|
||||
void ioport_unmap(void __iomem *addr)
|
||||
{
|
||||
sh_mv.mv_ioport_unmap(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_unmap);
|
||||
#endif /* CONFIG_GENERIC_IOMAP */
|
||||
165
arch/sh/kernel/iomap.c
Normal file
165
arch/sh/kernel/iomap.c
Normal file
|
|
@ -0,0 +1,165 @@
|
|||
/*
|
||||
* arch/sh/kernel/iomap.c
|
||||
*
|
||||
* Copyright (C) 2000 Niibe Yutaka
|
||||
* Copyright (C) 2005 - 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
unsigned int ioread8(void __iomem *addr)
|
||||
{
|
||||
return readb(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioread8);
|
||||
|
||||
unsigned int ioread16(void __iomem *addr)
|
||||
{
|
||||
return readw(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioread16);
|
||||
|
||||
unsigned int ioread16be(void __iomem *addr)
|
||||
{
|
||||
return be16_to_cpu(__raw_readw(addr));
|
||||
}
|
||||
EXPORT_SYMBOL(ioread16be);
|
||||
|
||||
unsigned int ioread32(void __iomem *addr)
|
||||
{
|
||||
return readl(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioread32);
|
||||
|
||||
unsigned int ioread32be(void __iomem *addr)
|
||||
{
|
||||
return be32_to_cpu(__raw_readl(addr));
|
||||
}
|
||||
EXPORT_SYMBOL(ioread32be);
|
||||
|
||||
void iowrite8(u8 val, void __iomem *addr)
|
||||
{
|
||||
writeb(val, addr);
|
||||
}
|
||||
EXPORT_SYMBOL(iowrite8);
|
||||
|
||||
void iowrite16(u16 val, void __iomem *addr)
|
||||
{
|
||||
writew(val, addr);
|
||||
}
|
||||
EXPORT_SYMBOL(iowrite16);
|
||||
|
||||
void iowrite16be(u16 val, void __iomem *addr)
|
||||
{
|
||||
__raw_writew(cpu_to_be16(val), addr);
|
||||
}
|
||||
EXPORT_SYMBOL(iowrite16be);
|
||||
|
||||
void iowrite32(u32 val, void __iomem *addr)
|
||||
{
|
||||
writel(val, addr);
|
||||
}
|
||||
EXPORT_SYMBOL(iowrite32);
|
||||
|
||||
void iowrite32be(u32 val, void __iomem *addr)
|
||||
{
|
||||
__raw_writel(cpu_to_be32(val), addr);
|
||||
}
|
||||
EXPORT_SYMBOL(iowrite32be);
|
||||
|
||||
/*
|
||||
* These are the "repeat MMIO read/write" functions.
|
||||
* Note the "__raw" accesses, since we don't want to
|
||||
* convert to CPU byte order. We write in "IO byte
|
||||
* order" (we also don't have IO barriers).
|
||||
*/
|
||||
static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
|
||||
{
|
||||
while (--count >= 0) {
|
||||
u8 data = __raw_readb(addr);
|
||||
*dst = data;
|
||||
dst++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
|
||||
{
|
||||
while (--count >= 0) {
|
||||
u16 data = __raw_readw(addr);
|
||||
*dst = data;
|
||||
dst++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
|
||||
{
|
||||
while (--count >= 0) {
|
||||
u32 data = __raw_readl(addr);
|
||||
*dst = data;
|
||||
dst++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
|
||||
{
|
||||
while (--count >= 0) {
|
||||
__raw_writeb(*src, addr);
|
||||
src++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
|
||||
{
|
||||
while (--count >= 0) {
|
||||
__raw_writew(*src, addr);
|
||||
src++;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
|
||||
{
|
||||
while (--count >= 0) {
|
||||
__raw_writel(*src, addr);
|
||||
src++;
|
||||
}
|
||||
}
|
||||
|
||||
void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
|
||||
{
|
||||
mmio_insb(addr, dst, count);
|
||||
}
|
||||
EXPORT_SYMBOL(ioread8_rep);
|
||||
|
||||
void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
|
||||
{
|
||||
mmio_insw(addr, dst, count);
|
||||
}
|
||||
EXPORT_SYMBOL(ioread16_rep);
|
||||
|
||||
void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
|
||||
{
|
||||
mmio_insl(addr, dst, count);
|
||||
}
|
||||
EXPORT_SYMBOL(ioread32_rep);
|
||||
|
||||
void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
|
||||
{
|
||||
mmio_outsb(addr, src, count);
|
||||
}
|
||||
EXPORT_SYMBOL(iowrite8_rep);
|
||||
|
||||
void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
|
||||
{
|
||||
mmio_outsw(addr, src, count);
|
||||
}
|
||||
EXPORT_SYMBOL(iowrite16_rep);
|
||||
|
||||
void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
|
||||
{
|
||||
mmio_outsl(addr, src, count);
|
||||
}
|
||||
EXPORT_SYMBOL(iowrite32_rep);
|
||||
43
arch/sh/kernel/ioport.c
Normal file
43
arch/sh/kernel/ioport.c
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* arch/sh/kernel/ioport.c
|
||||
*
|
||||
* Copyright (C) 2000 Niibe Yutaka
|
||||
* Copyright (C) 2005 - 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
const unsigned long sh_io_port_base __read_mostly = -1;
|
||||
EXPORT_SYMBOL(sh_io_port_base);
|
||||
|
||||
void __iomem *__ioport_map(unsigned long addr, unsigned int size)
|
||||
{
|
||||
if (sh_mv.mv_ioport_map)
|
||||
return sh_mv.mv_ioport_map(addr, size);
|
||||
|
||||
return (void __iomem *)(addr + sh_io_port_base);
|
||||
}
|
||||
EXPORT_SYMBOL(__ioport_map);
|
||||
|
||||
void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
||||
{
|
||||
void __iomem *ret;
|
||||
|
||||
ret = __ioport_map_trapped(port, nr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return __ioport_map(port, nr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_map);
|
||||
|
||||
void ioport_unmap(void __iomem *addr)
|
||||
{
|
||||
if (sh_mv.mv_ioport_unmap)
|
||||
sh_mv.mv_ioport_unmap(addr);
|
||||
}
|
||||
EXPORT_SYMBOL(ioport_unmap);
|
||||
|
|
@ -118,28 +118,6 @@ void __init sh_mv_setup(void)
|
|||
sh_mv.mv_##elem = generic_##elem; \
|
||||
} while (0)
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT
|
||||
|
||||
#ifdef P2SEG
|
||||
__set_io_port_base(P2SEG);
|
||||
#else
|
||||
__set_io_port_base(0);
|
||||
#endif
|
||||
|
||||
mv_set(inb); mv_set(inw); mv_set(inl);
|
||||
mv_set(outb); mv_set(outw); mv_set(outl);
|
||||
|
||||
mv_set(inb_p); mv_set(inw_p); mv_set(inl_p);
|
||||
mv_set(outb_p); mv_set(outw_p); mv_set(outl_p);
|
||||
|
||||
mv_set(insb); mv_set(insw); mv_set(insl);
|
||||
mv_set(outsb); mv_set(outsw); mv_set(outsl);
|
||||
|
||||
mv_set(ioport_map);
|
||||
mv_set(ioport_unmap);
|
||||
|
||||
#endif
|
||||
|
||||
mv_set(irq_demux);
|
||||
mv_set(mode_pins);
|
||||
mv_set(mem_init);
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ struct intc_hw_desc {
|
|||
unsigned int nr_subgroups;
|
||||
};
|
||||
|
||||
#define _INTC_ARRAY(a) a, a == NULL ? 0 : sizeof(a)/sizeof(*a)
|
||||
#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a)
|
||||
|
||||
#define INTC_HW_DESC(vectors, groups, mask_regs, \
|
||||
prio_regs, sense_regs, ack_regs) \
|
||||
|
|
|
|||
Loading…
Reference in a new issue