[ARM] 5477/1: Freescale STMP platform support [6/10]
Sources: common STMP3xxx platform support Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>wifi-calibration
dmitry pervushin
Russell King
parent
e317872ac5
commit
5cccd37ea1
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@ -0,0 +1,37 @@
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if ARCH_STMP3XXX
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menu "Freescale STMP3xxx implementations"
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choice
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prompt "Select STMP3xxx chip family"
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config ARCH_STMP37XX
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bool "Freescale SMTP37xx"
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select CPU_ARM926T
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---help---
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STMP37xx refers to 3700 through 3769 chips
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config ARCH_STMP378X
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bool "Freescale STMP378x"
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select CPU_ARM926T
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---help---
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STMP378x refers to 3780 through 3789 chips
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endchoice
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choice
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prompt "Select STMP3xxx board type"
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config MACH_STMP37XX
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depends on ARCH_STMP37XX
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bool "Freescale STMP37xx development board"
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config MACH_STMP378X
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depends on ARCH_STMP378X
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bool "Freescale STMP378x development board"
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endchoice
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endmenu
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endif
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@ -0,0 +1,5 @@
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#
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# Makefile for the linux kernel.
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#
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# Object file lists.
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obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,61 @@
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/*
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* Clock control driver for Freescale STMP37XX/STMP378X - internal header file
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*
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* Author: Vitaly Wool <vital@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
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#define __ARCH_ARM_STMX3XXX_CLOCK_H__
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#ifndef __ASSEMBLER__
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struct clk_ops {
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int (*enable) (struct clk *);
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int (*disable) (struct clk *);
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long (*get_rate) (struct clk *);
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long (*round_rate) (struct clk *, u32);
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int (*set_rate) (struct clk *, u32);
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int (*set_parent) (struct clk *, struct clk *);
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};
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struct clk {
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struct clk *parent;
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u32 rate;
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u32 flags;
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u8 scale_shift;
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u8 enable_shift;
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u8 bypass_shift;
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u8 busy_bit;
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s8 usage;
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int enable_wait;
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int enable_negate;
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u32 saved_div;
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void __iomem *enable_reg;
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void __iomem *scale_reg;
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void __iomem *bypass_reg;
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void __iomem *busy_reg;
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struct clk_ops *ops;
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};
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#endif /* __ASSEMBLER__ */
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/* Flags */
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#define RATE_PROPAGATES (1<<0)
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#define NEEDS_INITIALIZATION (1<<1)
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#define PARENT_SET_RATE (1<<2)
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#define FIXED_RATE (1<<3)
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#define ENABLED (1<<4)
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#define NEEDS_SET_PARENT (1<<5)
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#endif
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@ -0,0 +1,127 @@
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/*
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* Freescale STMP37XX/STMP378X core routines
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*
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* Embedded Alley Solutions, Inc <source@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/stmp3xxx.h>
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#include <mach/dma.h>
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#include <mach/regs-clkctrl.h>
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static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
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{
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u32 c;
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int timeout;
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/* the process of software reset of IP block is done
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in several steps:
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- clear SFTRST and wait for block is enabled;
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- clear clock gating (CLKGATE bit);
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- set the SFTRST again and wait for block is in reset;
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- clear SFTRST and wait for reset completion.
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*/
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c = __raw_readl(hwreg);
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c &= ~(1<<31); /* clear SFTRST */
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__raw_writel(c, hwreg);
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for (timeout = 1000000; timeout > 0; timeout--)
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/* still in SFTRST state ? */
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if ((__raw_readl(hwreg) & (1<<31)) == 0)
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break;
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if (timeout <= 0) {
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printk(KERN_ERR"%s(%p): timeout when enabling\n",
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__func__, hwreg);
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return -ETIME;
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}
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c = __raw_readl(hwreg);
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c &= ~(1<<30); /* clear CLKGATE */
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__raw_writel(c, hwreg);
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if (!just_enable) {
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c = __raw_readl(hwreg);
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c |= (1<<31); /* now again set SFTRST */
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__raw_writel(c, hwreg);
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for (timeout = 1000000; timeout > 0; timeout--)
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/* poll until CLKGATE set */
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if (__raw_readl(hwreg) & (1<<30))
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break;
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if (timeout <= 0) {
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printk(KERN_ERR"%s(%p): timeout when resetting\n",
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__func__, hwreg);
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return -ETIME;
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}
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c = __raw_readl(hwreg);
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c &= ~(1<<31); /* clear SFTRST */
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__raw_writel(c, hwreg);
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for (timeout = 1000000; timeout > 0; timeout--)
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/* still in SFTRST state ? */
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if ((__raw_readl(hwreg) & (1<<31)) == 0)
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break;
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if (timeout <= 0) {
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printk(KERN_ERR"%s(%p): timeout when enabling "
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"after reset\n", __func__, hwreg);
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return -ETIME;
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}
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c = __raw_readl(hwreg);
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c &= ~(1<<30); /* clear CLKGATE */
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__raw_writel(c, hwreg);
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}
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for (timeout = 1000000; timeout > 0; timeout--)
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/* still in SFTRST state ? */
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if ((__raw_readl(hwreg) & (1<<30)) == 0)
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break;
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if (timeout <= 0) {
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printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
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__func__, hwreg);
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return -ETIME;
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}
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return 0;
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}
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int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
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{
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int try = 10;
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int r;
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while (try--) {
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r = __stmp3xxx_reset_block(hwreg, just_enable);
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if (!r)
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break;
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pr_debug("%s: try %d failed\n", __func__, 10 - try);
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}
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return r;
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}
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EXPORT_SYMBOL(stmp3xxx_reset_block);
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struct platform_device stmp3xxx_dbguart = {
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.name = "stmp3xxx-dbguart",
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.id = -1,
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};
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void __init stmp3xxx_init(void)
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{
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/* Turn off auto-slow and other tricks */
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HW_CLKCTRL_HBUS_CLR(0x07f00000U);
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stmp3xxx_dma_init();
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}
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@ -0,0 +1,462 @@
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/*
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* DMA helper routines for Freescale STMP37XX/STMP378X
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*
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* Author: dmitry pervushin <dpervushin@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/dmapool.h>
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#include <linux/sysdev.h>
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#include <linux/cpufreq.h>
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#include <asm/page.h>
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#include <mach/dma.h>
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#include <mach/regs-apbx.h>
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#include <mach/regs-apbh.h>
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static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
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static const size_t pool_alignment = 8;
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static struct stmp3xxx_dma_user {
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void *pool;
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int inuse;
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const char *name;
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} channels[MAX_DMA_CHANNELS];
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static inline int dmach(int ch)
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{
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return ch % 16;
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}
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static inline int dmabus(int ch)
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{
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return ch / 16;
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}
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#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
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#define IS_USED(ch) (channels[ch].inuse)
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int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
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{
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struct stmp3xxx_dma_user *user;
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int err = 0;
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user = channels + ch;
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if (!IS_VALID_CHANNEL(ch)) {
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err = -ENODEV;
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goto out;
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}
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if (IS_USED(ch)) {
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err = -EBUSY;
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goto out;
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}
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/* Create a pool to allocate dma commands from */
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user->pool = dma_pool_create(name, dev, pool_item_size,
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pool_alignment, PAGE_SIZE);
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if (user->pool == NULL) {
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err = -ENOMEM;
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goto out;
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}
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user->name = name;
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user->inuse++;
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out:
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return err;
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}
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EXPORT_SYMBOL(stmp3xxx_dma_request);
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int stmp3xxx_dma_release(int ch)
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{
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struct stmp3xxx_dma_user *user = channels + ch;
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int err = 0;
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if (!IS_VALID_CHANNEL(ch)) {
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err = -ENODEV;
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goto out;
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}
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if (!IS_USED(ch)) {
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err = -EBUSY;
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goto out;
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}
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BUG_ON(user->pool == NULL);
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dma_pool_destroy(user->pool);
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user->inuse--;
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out:
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return err;
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}
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EXPORT_SYMBOL(stmp3xxx_dma_release);
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int stmp3xxx_dma_read_semaphore(int channel)
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{
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int sem = -1;
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switch (dmabus(channel)) {
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case STMP3XXX_BUS_APBH:
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sem =
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(HW_APBH_CHn_SEMA_RD(dmach(channel)) &
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BM_APBH_CHn_SEMA_PHORE) >> BP_APBH_CHn_SEMA_PHORE;
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break;
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case STMP3XXX_BUS_APBX:
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sem =
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(HW_APBX_CHn_SEMA_RD(dmach(channel)) &
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BM_APBX_CHn_SEMA_PHORE) >> BP_APBX_CHn_SEMA_PHORE;
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break;
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default:
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BUG();
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}
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return sem;
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}
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EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
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int stmp3xxx_dma_allocate_command(int channel,
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struct stmp3xxx_dma_descriptor *descriptor)
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{
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struct stmp3xxx_dma_user *user = channels + channel;
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int err = 0;
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if (!IS_VALID_CHANNEL(channel)) {
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err = -ENODEV;
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goto out;
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}
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if (!IS_USED(channel)) {
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err = -EBUSY;
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goto out;
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}
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if (descriptor == NULL) {
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err = -EINVAL;
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goto out;
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}
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/* Allocate memory for a command from the buffer */
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descriptor->command =
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dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
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/* Check it worked */
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if (!descriptor->command) {
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err = -ENOMEM;
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goto out;
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}
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memset(descriptor->command, 0, pool_item_size);
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out:
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WARN_ON(err);
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return err;
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}
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EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
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int stmp3xxx_dma_free_command(int channel,
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struct stmp3xxx_dma_descriptor *descriptor)
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{
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int err = 0;
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if (!IS_VALID_CHANNEL(channel)) {
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err = -ENODEV;
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goto out;
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}
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if (!IS_USED(channel)) {
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err = -EBUSY;
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goto out;
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}
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/* Return the command memory to the pool */
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dma_pool_free(channels[channel].pool, descriptor->command,
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descriptor->handle);
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/* Initialise descriptor so we're not tempted to use it */
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descriptor->command = NULL;
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descriptor->handle = 0;
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descriptor->virtual_buf_ptr = NULL;
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descriptor->next_descr = NULL;
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WARN_ON(err);
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out:
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return err;
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}
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EXPORT_SYMBOL(stmp3xxx_dma_free_command);
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void stmp3xxx_dma_go(int channel,
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struct stmp3xxx_dma_descriptor *head, u32 semaphore)
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{
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int ch = dmach(channel);
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switch (dmabus(channel)) {
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case STMP3XXX_BUS_APBH:
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/* Set next command */
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HW_APBH_CHn_NXTCMDAR_WR(ch, head->handle);
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/* Set counting semaphore (kicks off transfer). Assumes
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peripheral has been set up correctly */
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HW_APBH_CHn_SEMA_WR(ch, semaphore);
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break;
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case STMP3XXX_BUS_APBX:
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/* Set next command */
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HW_APBX_CHn_NXTCMDAR_WR(ch, head->handle);
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/* Set counting semaphore (kicks off transfer). Assumes
|
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peripheral has been set up correctly */
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HW_APBX_CHn_SEMA_WR(ch, semaphore);
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break;
|
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}
|
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}
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EXPORT_SYMBOL(stmp3xxx_dma_go);
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|
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int stmp3xxx_dma_running(int channel)
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{
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switch (dmabus(channel)) {
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case STMP3XXX_BUS_APBH:
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return HW_APBH_CHn_SEMA_RD(dmach(channel)) &
|
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BM_APBH_CHn_SEMA_PHORE;
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|
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case STMP3XXX_BUS_APBX:
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return HW_APBX_CHn_SEMA_RD(dmach(channel)) &
|
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BM_APBX_CHn_SEMA_PHORE;
|
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|
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default:
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BUG();
|
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return 0;
|
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}
|
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}
|
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EXPORT_SYMBOL(stmp3xxx_dma_running);
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|
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/*
|
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* Circular dma chain management
|
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*/
|
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void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
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{
|
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int i;
|
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|
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for (i = 0; i < chain->total_count; i++)
|
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stmp3xxx_dma_free_command(
|
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STMP3xxx_DMA(chain->channel, chain->bus),
|
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&chain->chain[i]);
|
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}
|
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EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
|
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|
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int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
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struct stmp3xxx_dma_descriptor descriptors[],
|
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unsigned items)
|
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{
|
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int i;
|
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int err = 0;
|
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|
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if (items == 0)
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return err;
|
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|
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for (i = 0; i < items; i++) {
|
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err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
|
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if (err) {
|
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WARN_ON(err);
|
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/*
|
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* Couldn't allocate the whole chain.
|
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* deallocate what has been allocated
|
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*/
|
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if (i) {
|
||||
do {
|
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stmp3xxx_dma_free_command(ch,
|
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&descriptors
|
||||
[i]);
|
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} while (i-- >= 0);
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}
|
||||
return err;
|
||||
}
|
||||
|
||||
/* link them! */
|
||||
if (i > 0) {
|
||||
descriptors[i - 1].next_descr = &descriptors[i];
|
||||
descriptors[i - 1].command->next =
|
||||
descriptors[i].handle;
|
||||
}
|
||||
}
|
||||
|
||||
/* make list circular */
|
||||
descriptors[items - 1].next_descr = &descriptors[0];
|
||||
descriptors[items - 1].command->next = descriptors[0].handle;
|
||||
|
||||
chain->total_count = items;
|
||||
chain->chain = descriptors;
|
||||
chain->free_index = 0;
|
||||
chain->active_index = 0;
|
||||
chain->cooked_index = 0;
|
||||
chain->free_count = items;
|
||||
chain->active_count = 0;
|
||||
chain->cooked_count = 0;
|
||||
chain->bus = dmabus(ch);
|
||||
chain->channel = dmach(ch);
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
|
||||
|
||||
void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
|
||||
{
|
||||
BUG_ON(stmp3xxx_dma_running(STMP3xxx_DMA(chain->channel, chain->bus)) >
|
||||
0);
|
||||
chain->free_index = 0;
|
||||
chain->active_index = 0;
|
||||
chain->cooked_index = 0;
|
||||
chain->free_count = chain->total_count;
|
||||
chain->active_count = 0;
|
||||
chain->cooked_count = 0;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
|
||||
|
||||
void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
|
||||
unsigned count)
|
||||
{
|
||||
BUG_ON(chain->cooked_count < count);
|
||||
|
||||
chain->cooked_count -= count;
|
||||
chain->cooked_index += count;
|
||||
chain->cooked_index %= chain->total_count;
|
||||
chain->free_count += count;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp37xx_circ_advance_free);
|
||||
|
||||
void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
|
||||
unsigned count)
|
||||
{
|
||||
BUG_ON(chain->free_count < count);
|
||||
|
||||
chain->free_count -= count;
|
||||
chain->free_index += count;
|
||||
chain->free_index %= chain->total_count;
|
||||
chain->active_count += count;
|
||||
|
||||
switch (chain->bus) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
/* Set counting semaphore (kicks off transfer). Assumes
|
||||
peripheral has been set up correctly */
|
||||
HW_APBH_CHn_SEMA_CLR(chain->channel,
|
||||
BM_APBH_CHn_SEMA_INCREMENT_SEMA);
|
||||
HW_APBH_CHn_SEMA_SET(chain->channel,
|
||||
BF_APBH_CHn_SEMA_INCREMENT_SEMA(count));
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
/* Set counting semaphore (kicks off transfer). Assumes
|
||||
peripheral has been set up correctly */
|
||||
HW_APBX_CHn_SEMA_CLR(chain->channel,
|
||||
BM_APBX_CHn_SEMA_INCREMENT_SEMA);
|
||||
HW_APBX_CHn_SEMA_SET(chain->channel,
|
||||
BF_APBX_CHn_SEMA_INCREMENT_SEMA(count));
|
||||
break;
|
||||
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp37xx_circ_advance_active);
|
||||
|
||||
unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
|
||||
{
|
||||
unsigned cooked;
|
||||
|
||||
cooked = chain->active_count -
|
||||
stmp3xxx_dma_read_semaphore(STMP3xxx_DMA(chain->channel, chain->bus));
|
||||
|
||||
chain->active_count -= cooked;
|
||||
chain->active_index += cooked;
|
||||
chain->active_index %= chain->total_count;
|
||||
|
||||
chain->cooked_count += cooked;
|
||||
|
||||
return cooked;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
|
||||
|
||||
void stmp3xxx_dma_set_alt_target(int channel, int function)
|
||||
{
|
||||
#if defined(CONFIG_ARCH_STMP37XX)
|
||||
unsigned bits = 4;
|
||||
#elif defined(CONFIG_ARCH_STMP378X)
|
||||
unsigned bits = 2;
|
||||
#else
|
||||
#error wrong arch
|
||||
#endif
|
||||
int shift = dmach(channel) * bits;
|
||||
unsigned mask = (1<<bits) - 1;
|
||||
|
||||
BUG_ON(function < 0 || function >= (1<<bits));
|
||||
pr_debug("%s: channel = %d, using mask %x, "
|
||||
"shift = %d\n", __func__, channel, mask, shift);
|
||||
|
||||
switch (dmabus(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
HW_APBH_DEVSEL_CLR(mask<<shift);
|
||||
HW_APBH_DEVSEL_SET(function<<shift);
|
||||
break;
|
||||
case STMP3XXX_BUS_APBX:
|
||||
HW_APBX_DEVSEL_CLR(mask<<shift);
|
||||
HW_APBX_DEVSEL_SET(function<<shift);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
|
||||
|
||||
void stmp3xxx_dma_suspend(void)
|
||||
{
|
||||
HW_APBH_CTRL0_SET(BM_APBH_CTRL0_CLKGATE);
|
||||
HW_APBX_CTRL0_SET(BM_APBX_CTRL0_CLKGATE);
|
||||
}
|
||||
|
||||
void stmp3xxx_dma_resume(void)
|
||||
{
|
||||
HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST);
|
||||
HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
|
||||
struct dma_notifier_block {
|
||||
struct notifier_block nb;
|
||||
void *data;
|
||||
};
|
||||
|
||||
static int dma_cpufreq_notifier(struct notifier_block *self,
|
||||
unsigned long phase, void *p)
|
||||
{
|
||||
switch (phase) {
|
||||
case CPUFREQ_POSTCHANGE:
|
||||
stmp3xxx_dma_resume();
|
||||
break;
|
||||
|
||||
case CPUFREQ_PRECHANGE:
|
||||
stmp3xxx_dma_suspend();
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct dma_notifier_block dma_cpufreq_nb = {
|
||||
.nb = {
|
||||
.notifier_call = dma_cpufreq_notifier,
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_CPU_FREQ */
|
||||
|
||||
void __init stmp3xxx_dma_init(void)
|
||||
{
|
||||
HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST);
|
||||
HW_APBX_CTRL0_CLR(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST);
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
cpufreq_register_notifier(&dma_cpufreq_nb.nb,
|
||||
CPUFREQ_TRANSITION_NOTIFIER);
|
||||
#endif /* CONFIG_CPU_FREQ */
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X common interrupt handling code
|
||||
*
|
||||
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/sysdev.h>
|
||||
|
||||
#include <mach/stmp3xxx.h>
|
||||
#include <mach/regs-icoll.h>
|
||||
|
||||
void __init stmp3xxx_init_irq(struct irq_chip *chip)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
/* Reset the interrupt controller */
|
||||
HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_CLKGATE);
|
||||
udelay(10);
|
||||
HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST);
|
||||
udelay(10);
|
||||
HW_ICOLL_CTRL_SET(BM_ICOLL_CTRL_SFTRST);
|
||||
while (!(HW_ICOLL_CTRL_RD() & BM_ICOLL_CTRL_CLKGATE))
|
||||
continue;
|
||||
HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_CLKGATE);
|
||||
|
||||
/* Disable all interrupts initially */
|
||||
for (i = 0; i < NR_REAL_IRQS; i++) {
|
||||
chip->mask(i);
|
||||
set_irq_chip(i, chip);
|
||||
set_irq_handler(i, handle_level_irq);
|
||||
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
|
||||
}
|
||||
|
||||
/* Ensure vector is cleared */
|
||||
HW_ICOLL_LEVELACK_WR(1);
|
||||
HW_ICOLL_LEVELACK_WR(2);
|
||||
HW_ICOLL_LEVELACK_WR(4);
|
||||
HW_ICOLL_LEVELACK_WR(8);
|
||||
|
||||
HW_ICOLL_VECTOR_WR(0);
|
||||
/* Barrier */
|
||||
(void) HW_ICOLL_STAT_RD();
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,545 @@
|
|||
/*
|
||||
* Freescale STMP378X/STMP378X Pin Multiplexing
|
||||
*
|
||||
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/regs-pinctrl.h>
|
||||
#include <mach/pins.h>
|
||||
#include <mach/pinmux.h>
|
||||
|
||||
#define NR_BANKS ARRAY_SIZE(pinmux_banks)
|
||||
static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
|
||||
[0] = {
|
||||
.hw_muxsel = {
|
||||
HW_PINCTRL_MUXSEL0_ADDR,
|
||||
HW_PINCTRL_MUXSEL1_ADDR
|
||||
},
|
||||
.hw_drive = {
|
||||
HW_PINCTRL_DRIVE0_ADDR,
|
||||
HW_PINCTRL_DRIVE1_ADDR,
|
||||
HW_PINCTRL_DRIVE2_ADDR,
|
||||
HW_PINCTRL_DRIVE3_ADDR
|
||||
},
|
||||
.hw_pull = HW_PINCTRL_PULL0_ADDR,
|
||||
.functions = { 0x0, 0x1, 0x2, 0x3 },
|
||||
.strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
|
||||
|
||||
.hw_gpio_read = HW_PINCTRL_DIN0_ADDR,
|
||||
.hw_gpio_set = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_SET,
|
||||
.hw_gpio_clr = HW_PINCTRL_DOUT0_ADDR + HW_STMP3xxx_CLR,
|
||||
.hw_gpio_doe = HW_PINCTRL_DOE0_ADDR,
|
||||
.irq = IRQ_GPIO0,
|
||||
|
||||
.pin2irq = HW_PINCTRL_PIN2IRQ0_ADDR,
|
||||
.irqstat = HW_PINCTRL_IRQSTAT0_ADDR,
|
||||
.irqlevel = HW_PINCTRL_IRQLEVEL0_ADDR,
|
||||
.irqpolarity = HW_PINCTRL_IRQPOL0_ADDR,
|
||||
.irqen = HW_PINCTRL_IRQEN0_ADDR,
|
||||
},
|
||||
[1] = {
|
||||
.hw_muxsel = {
|
||||
HW_PINCTRL_MUXSEL2_ADDR,
|
||||
HW_PINCTRL_MUXSEL3_ADDR
|
||||
},
|
||||
.hw_drive = {
|
||||
HW_PINCTRL_DRIVE4_ADDR,
|
||||
HW_PINCTRL_DRIVE5_ADDR,
|
||||
HW_PINCTRL_DRIVE6_ADDR,
|
||||
HW_PINCTRL_DRIVE7_ADDR
|
||||
},
|
||||
.hw_pull = HW_PINCTRL_PULL1_ADDR,
|
||||
.functions = { 0x0, 0x1, 0x2, 0x3 },
|
||||
.strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
|
||||
|
||||
.hw_gpio_read = HW_PINCTRL_DIN1_ADDR,
|
||||
.hw_gpio_set = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_SET,
|
||||
.hw_gpio_clr = HW_PINCTRL_DOUT1_ADDR + HW_STMP3xxx_CLR,
|
||||
.hw_gpio_doe = HW_PINCTRL_DOE1_ADDR,
|
||||
.irq = IRQ_GPIO1,
|
||||
|
||||
.pin2irq = HW_PINCTRL_PIN2IRQ1_ADDR,
|
||||
.irqstat = HW_PINCTRL_IRQSTAT1_ADDR,
|
||||
.irqlevel = HW_PINCTRL_IRQLEVEL1_ADDR,
|
||||
.irqpolarity = HW_PINCTRL_IRQPOL1_ADDR,
|
||||
.irqen = HW_PINCTRL_IRQEN1_ADDR,
|
||||
},
|
||||
[2] = {
|
||||
.hw_muxsel = {
|
||||
HW_PINCTRL_MUXSEL4_ADDR,
|
||||
HW_PINCTRL_MUXSEL5_ADDR,
|
||||
},
|
||||
.hw_drive = {
|
||||
HW_PINCTRL_DRIVE8_ADDR,
|
||||
HW_PINCTRL_DRIVE9_ADDR,
|
||||
HW_PINCTRL_DRIVE10_ADDR,
|
||||
HW_PINCTRL_DRIVE11_ADDR,
|
||||
},
|
||||
.hw_pull = HW_PINCTRL_PULL2_ADDR,
|
||||
.functions = { 0x0, 0x1, 0x2, 0x3 },
|
||||
.strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
|
||||
|
||||
.hw_gpio_read = HW_PINCTRL_DIN2_ADDR,
|
||||
.hw_gpio_set = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_SET,
|
||||
.hw_gpio_clr = HW_PINCTRL_DOUT2_ADDR + HW_STMP3xxx_CLR,
|
||||
.hw_gpio_doe = HW_PINCTRL_DOE2_ADDR,
|
||||
.irq = IRQ_GPIO2,
|
||||
|
||||
.pin2irq = HW_PINCTRL_PIN2IRQ2_ADDR,
|
||||
.irqstat = HW_PINCTRL_IRQSTAT2_ADDR,
|
||||
.irqlevel = HW_PINCTRL_IRQLEVEL2_ADDR,
|
||||
.irqpolarity = HW_PINCTRL_IRQPOL2_ADDR,
|
||||
.irqen = HW_PINCTRL_IRQEN2_ADDR,
|
||||
},
|
||||
[3] = {
|
||||
.hw_muxsel = {
|
||||
HW_PINCTRL_MUXSEL6_ADDR,
|
||||
HW_PINCTRL_MUXSEL7_ADDR,
|
||||
},
|
||||
.hw_drive = {
|
||||
HW_PINCTRL_DRIVE12_ADDR,
|
||||
HW_PINCTRL_DRIVE13_ADDR,
|
||||
HW_PINCTRL_DRIVE14_ADDR,
|
||||
NULL,
|
||||
},
|
||||
.hw_pull = HW_PINCTRL_PULL3_ADDR,
|
||||
.functions = {0x0, 0x1, 0x2, 0x3},
|
||||
.strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
|
||||
},
|
||||
};
|
||||
|
||||
static inline struct stmp3xxx_pinmux_bank *
|
||||
stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
|
||||
{
|
||||
unsigned b, p;
|
||||
|
||||
b = STMP3XXX_PINID_TO_BANK(id);
|
||||
p = STMP3XXX_PINID_TO_PINNUM(id);
|
||||
BUG_ON(b >= NR_BANKS);
|
||||
if (bank)
|
||||
*bank = b;
|
||||
if (pin)
|
||||
*pin = p;
|
||||
return &pinmux_banks[b];
|
||||
}
|
||||
|
||||
/* Check if requested pin is owned by caller */
|
||||
static int stmp3xxx_check_pin(unsigned id, const char *label)
|
||||
{
|
||||
unsigned pin;
|
||||
struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
|
||||
|
||||
if (!test_bit(pin, &pm->pin_map)) {
|
||||
printk(KERN_WARNING
|
||||
"%s: Accessing free pin %x, caller %s\n",
|
||||
__func__, id, label);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (label && pm->pin_labels[pin] &&
|
||||
strcmp(label, pm->pin_labels[pin])) {
|
||||
printk(KERN_WARNING
|
||||
"%s: Wrong pin owner %x, caller %s owner %s\n",
|
||||
__func__, id, label, pm->pin_labels[pin]);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
|
||||
const char *label)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pbank;
|
||||
void __iomem *hwdrive;
|
||||
u32 shift, val;
|
||||
u32 bank, pin;
|
||||
|
||||
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
|
||||
pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
|
||||
bank, pin, strength);
|
||||
|
||||
hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
|
||||
shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
|
||||
val = pbank->strengths[strength];
|
||||
if (val == 0xff) {
|
||||
printk(KERN_WARNING
|
||||
"%s: strength is not supported for bank %d, caller %s",
|
||||
__func__, bank, label);
|
||||
return;
|
||||
}
|
||||
|
||||
if (stmp3xxx_check_pin(id, label))
|
||||
return;
|
||||
|
||||
pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
|
||||
val << shift, hwdrive);
|
||||
__raw_writel(HW_DRIVE_PINDRV_MASK << shift, hwdrive + HW_STMP3xxx_CLR);
|
||||
__raw_writel(val << shift, hwdrive + HW_STMP3xxx_SET);
|
||||
}
|
||||
|
||||
void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
|
||||
const char *label)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pbank;
|
||||
void __iomem *hwdrive;
|
||||
u32 shift;
|
||||
u32 bank, pin;
|
||||
|
||||
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
|
||||
pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
|
||||
bank, pin, voltage);
|
||||
|
||||
hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
|
||||
shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
|
||||
|
||||
if (stmp3xxx_check_pin(id, label))
|
||||
return;
|
||||
|
||||
pr_debug("%s: changing 0x%x bit in 0x%p register\n",
|
||||
__func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
|
||||
if (voltage == PIN_1_8V)
|
||||
__raw_writel(HW_DRIVE_PINV_MASK << shift,
|
||||
hwdrive + HW_STMP3xxx_CLR);
|
||||
else
|
||||
__raw_writel(HW_DRIVE_PINV_MASK << shift,
|
||||
hwdrive + HW_STMP3xxx_SET);
|
||||
}
|
||||
|
||||
void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pbank;
|
||||
void __iomem *hwpull;
|
||||
u32 bank, pin;
|
||||
|
||||
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
|
||||
pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
|
||||
bank, pin, enable);
|
||||
|
||||
hwpull = pbank->hw_pull;
|
||||
|
||||
if (stmp3xxx_check_pin(id, label))
|
||||
return;
|
||||
|
||||
pr_debug("%s: changing 0x%x bit in 0x%p register\n",
|
||||
__func__, 1 << pin, hwpull);
|
||||
__raw_writel(1 << pin,
|
||||
hwpull + (enable ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR));
|
||||
}
|
||||
|
||||
int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pbank;
|
||||
u32 bank, pin;
|
||||
int ret = 0;
|
||||
|
||||
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
|
||||
pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
|
||||
bank, pin, fun);
|
||||
|
||||
if (test_bit(pin, &pbank->pin_map)) {
|
||||
printk(KERN_WARNING
|
||||
"%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
|
||||
__func__, bank, pin, label, pbank->pin_labels[pin]);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
set_bit(pin, &pbank->pin_map);
|
||||
pbank->pin_labels[pin] = label;
|
||||
|
||||
stmp3xxx_set_pin_type(id, fun);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pbank;
|
||||
void __iomem *hwmux;
|
||||
u32 shift, val;
|
||||
u32 bank, pin;
|
||||
|
||||
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
|
||||
|
||||
hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
|
||||
shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
|
||||
|
||||
val = pbank->functions[fun];
|
||||
shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
|
||||
pr_debug("%s: writing 0x%x to 0x%p register\n",
|
||||
__func__, val << shift, hwmux);
|
||||
__raw_writel(HW_MUXSEL_PINFUN_MASK << shift, hwmux + HW_STMP3xxx_CLR);
|
||||
__raw_writel(val << shift, hwmux + HW_STMP3xxx_SET);
|
||||
}
|
||||
|
||||
void stmp3xxx_release_pin(unsigned id, const char *label)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pbank;
|
||||
u32 bank, pin;
|
||||
|
||||
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
|
||||
pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
|
||||
|
||||
if (stmp3xxx_check_pin(id, label))
|
||||
return;
|
||||
|
||||
clear_bit(pin, &pbank->pin_map);
|
||||
pbank->pin_labels[pin] = NULL;
|
||||
}
|
||||
|
||||
int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
|
||||
{
|
||||
struct pin_desc *pin;
|
||||
int p;
|
||||
int err = 0;
|
||||
|
||||
/* Allocate and configure pins */
|
||||
for (p = 0; p < pin_group->nr_pins; p++) {
|
||||
pr_debug("%s: #%d\n", __func__, p);
|
||||
pin = &pin_group->pins[p];
|
||||
|
||||
err = stmp3xxx_request_pin(pin->id, pin->fun, label);
|
||||
if (err)
|
||||
goto out_err;
|
||||
|
||||
stmp3xxx_pin_strength(pin->id, pin->strength, label);
|
||||
stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
|
||||
stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out_err:
|
||||
/* Release allocated pins in case of error */
|
||||
while (--p >= 0) {
|
||||
pr_debug("%s: releasing #%d\n", __func__, p);
|
||||
stmp3xxx_release_pin(pin_group->pins[p].id, label);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_request_pin_group);
|
||||
|
||||
void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
|
||||
{
|
||||
struct pin_desc *pin;
|
||||
int p;
|
||||
|
||||
for (p = 0; p < pin_group->nr_pins; p++) {
|
||||
pin = &pin_group->pins[p];
|
||||
stmp3xxx_release_pin(pin->id, label);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_release_pin_group);
|
||||
|
||||
static int stmp3xxx_irq_to_gpio(int irq,
|
||||
struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm;
|
||||
|
||||
for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
|
||||
if (pm->virq <= irq && irq < pm->virq + 32) {
|
||||
*bank = pm;
|
||||
*gpio = irq - pm->virq;
|
||||
return 0;
|
||||
}
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static int stmp3xxx_set_irqtype(unsigned irq, unsigned type)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm;
|
||||
unsigned gpio;
|
||||
int l, p;
|
||||
|
||||
stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
|
||||
switch (type) {
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
l = 0; p = 1; break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
l = 0; p = 0; break;
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
l = 1; p = 1; break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
l = 1; p = 0; break;
|
||||
default:
|
||||
pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
|
||||
__func__, type);
|
||||
return -ENXIO;
|
||||
}
|
||||
__raw_writel(1 << gpio,
|
||||
pm->irqlevel + (l ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR));
|
||||
__raw_writel(1 << gpio,
|
||||
pm->irqpolarity + (p ? HW_STMP3xxx_SET : HW_STMP3xxx_CLR));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void stmp3xxx_pin_ack_irq(unsigned irq)
|
||||
{
|
||||
u32 stat;
|
||||
struct stmp3xxx_pinmux_bank *pm;
|
||||
unsigned gpio;
|
||||
|
||||
stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
|
||||
stat = __raw_readl(pm->irqstat) & (1<<gpio);
|
||||
__raw_writel(stat, pm->irqstat + HW_STMP3xxx_CLR);
|
||||
}
|
||||
|
||||
static void stmp3xxx_pin_mask_irq(unsigned irq)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm;
|
||||
unsigned gpio;
|
||||
|
||||
stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
|
||||
__raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_CLR);
|
||||
__raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_CLR);
|
||||
}
|
||||
|
||||
static void stmp3xxx_pin_unmask_irq(unsigned irq)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm;
|
||||
unsigned gpio;
|
||||
|
||||
stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
|
||||
__raw_writel(1 << gpio, pm->irqen + HW_STMP3xxx_SET);
|
||||
__raw_writel(1 << gpio, pm->pin2irq + HW_STMP3xxx_SET);
|
||||
}
|
||||
|
||||
static inline
|
||||
struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
|
||||
{
|
||||
return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
|
||||
}
|
||||
|
||||
static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
|
||||
return pm->virq + offset;
|
||||
}
|
||||
|
||||
static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
|
||||
unsigned v;
|
||||
|
||||
v = __raw_readl(pm->hw_gpio_read) & (1 << offset);
|
||||
return v ? 1 : 0;
|
||||
}
|
||||
|
||||
static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
|
||||
|
||||
__raw_writel(1 << offset, v ? pm->hw_gpio_set : pm->hw_gpio_clr);
|
||||
}
|
||||
|
||||
static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
|
||||
|
||||
__raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_SET);
|
||||
stmp3xxx_gpio_set(chip, offset, v);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
|
||||
|
||||
__raw_writel(1 << offset, pm->hw_gpio_doe + HW_STMP3xxx_CLR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
|
||||
}
|
||||
|
||||
static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
stmp3xxx_release_pin(chip->base + offset, "gpio");
|
||||
}
|
||||
|
||||
static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
|
||||
{
|
||||
struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq);
|
||||
int gpio_irq = pm->virq;
|
||||
u32 stat = __raw_readl(pm->irqstat);
|
||||
|
||||
while (stat) {
|
||||
if (stat & 1)
|
||||
irq_desc[gpio_irq].handle_irq(gpio_irq,
|
||||
&irq_desc[gpio_irq]);
|
||||
gpio_irq++;
|
||||
stat >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
static struct irq_chip gpio_irq_chip = {
|
||||
.ack = stmp3xxx_pin_ack_irq,
|
||||
.mask = stmp3xxx_pin_mask_irq,
|
||||
.unmask = stmp3xxx_pin_unmask_irq,
|
||||
.set_type = stmp3xxx_set_irqtype,
|
||||
};
|
||||
|
||||
int __init stmp3xxx_pinmux_init(int virtual_irq_start)
|
||||
{
|
||||
int b, r = 0;
|
||||
struct stmp3xxx_pinmux_bank *pm;
|
||||
int virq;
|
||||
|
||||
for (b = 0; b < 3; b++) {
|
||||
/* only banks 0,1,2 are allowed to GPIO */
|
||||
pm = pinmux_banks + b;
|
||||
pm->chip.base = 32 * b;
|
||||
pm->chip.ngpio = 32;
|
||||
pm->chip.owner = THIS_MODULE;
|
||||
pm->chip.can_sleep = 1;
|
||||
pm->chip.exported = 1;
|
||||
pm->chip.to_irq = stmp3xxx_gpio_to_irq;
|
||||
pm->chip.direction_input = stmp3xxx_gpio_input;
|
||||
pm->chip.direction_output = stmp3xxx_gpio_output;
|
||||
pm->chip.get = stmp3xxx_gpio_get;
|
||||
pm->chip.set = stmp3xxx_gpio_set;
|
||||
pm->chip.request = stmp3xxx_gpio_request;
|
||||
pm->chip.free = stmp3xxx_gpio_free;
|
||||
pm->virq = virtual_irq_start + b * 32;
|
||||
|
||||
for (virq = pm->virq; virq < pm->virq; virq++) {
|
||||
gpio_irq_chip.mask(virq);
|
||||
set_irq_chip(virq, &gpio_irq_chip);
|
||||
set_irq_handler(virq, handle_level_irq);
|
||||
set_irq_flags(virq, IRQF_VALID);
|
||||
}
|
||||
r = gpiochip_add(&pm->chip);
|
||||
if (r < 0)
|
||||
break;
|
||||
set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq);
|
||||
set_irq_data(pm->irq, pm);
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
MODULE_AUTHOR("Vladislav Buzov");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/*
|
||||
* System timer for Freescale STMP37XX/STMP378X
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/stmp3xxx.h>
|
||||
#include <mach/regs-timrot.h>
|
||||
|
||||
static irqreturn_t
|
||||
stmp3xxx_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *c = dev_id;
|
||||
|
||||
if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) {
|
||||
HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
|
||||
c->event_handler(c);
|
||||
} else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) {
|
||||
HW_TIMROT_TIMCTRLn_CLR(1, (1<<15));
|
||||
HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN);
|
||||
HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static cycle_t stmp3xxx_clock_read(void)
|
||||
{
|
||||
return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16);
|
||||
}
|
||||
|
||||
static int
|
||||
stmp3xxx_timrot_set_next_event(unsigned long delta,
|
||||
struct clock_event_device *dev)
|
||||
{
|
||||
HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
stmp3xxx_timrot_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *dev)
|
||||
{
|
||||
}
|
||||
|
||||
static struct clock_event_device ckevt_timrot = {
|
||||
.name = "timrot",
|
||||
.features = CLOCK_EVT_FEAT_ONESHOT,
|
||||
.shift = 32,
|
||||
.set_next_event = stmp3xxx_timrot_set_next_event,
|
||||
.set_mode = stmp3xxx_timrot_set_mode,
|
||||
};
|
||||
|
||||
static struct clocksource cksrc_stmp3xxx = {
|
||||
.name = "cksrc_stmp3xxx",
|
||||
.rating = 250,
|
||||
.read = stmp3xxx_clock_read,
|
||||
.mask = CLOCKSOURCE_MASK(16),
|
||||
.shift = 10,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static struct irqaction stmp3xxx_timer_irq = {
|
||||
.name = "stmp3xxx_timer",
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER,
|
||||
.handler = stmp3xxx_timer_interrupt,
|
||||
.dev_id = &ckevt_timrot,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Set up timer interrupt, and return the current time in seconds.
|
||||
*/
|
||||
static void __init stmp3xxx_init_timer(void)
|
||||
{
|
||||
cksrc_stmp3xxx.mult = clocksource_hz2mult(CLOCK_TICK_RATE,
|
||||
cksrc_stmp3xxx.shift);
|
||||
ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
|
||||
ckevt_timrot.shift);
|
||||
ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
|
||||
ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
|
||||
ckevt_timrot.cpumask = cpumask_of(0);
|
||||
|
||||
HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
|
||||
BM_TIMROT_ROTCTRL_CLKGATE);
|
||||
HW_TIMROT_TIMCOUNTn_WR(0, 0);
|
||||
HW_TIMROT_TIMCOUNTn_WR(1, 0);
|
||||
|
||||
HW_TIMROT_TIMCTRLn_WR(0,
|
||||
(BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */
|
||||
BF_TIMROT_TIMCTRLn_PRESCALE(0) |
|
||||
BM_TIMROT_TIMCTRLn_RELOAD |
|
||||
BM_TIMROT_TIMCTRLn_UPDATE |
|
||||
BM_TIMROT_TIMCTRLn_IRQ_EN));
|
||||
HW_TIMROT_TIMCTRLn_WR(1,
|
||||
(BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */
|
||||
BF_TIMROT_TIMCTRLn_PRESCALE(0) |
|
||||
BM_TIMROT_TIMCTRLn_RELOAD |
|
||||
BM_TIMROT_TIMCTRLn_UPDATE));
|
||||
|
||||
HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
|
||||
HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
|
||||
|
||||
setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
|
||||
|
||||
clocksource_register(&cksrc_stmp3xxx);
|
||||
clockevents_register_device(&ckevt_timrot);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
void stmp3xxx_suspend_timer(void)
|
||||
{
|
||||
HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN);
|
||||
HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
|
||||
HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE);
|
||||
}
|
||||
|
||||
void stmp3xxx_resume_timer(void)
|
||||
{
|
||||
HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
|
||||
BM_TIMROT_ROTCTRL_CLKGATE);
|
||||
|
||||
|
||||
HW_TIMROT_TIMCTRLn_WR(0,
|
||||
(BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */
|
||||
BF_TIMROT_TIMCTRLn_PRESCALE(0) |
|
||||
BM_TIMROT_TIMCTRLn_UPDATE |
|
||||
BM_TIMROT_TIMCTRLn_IRQ_EN));
|
||||
HW_TIMROT_TIMCTRLn_WR(1,
|
||||
(BF_TIMROT_TIMCTRLn_SELECT(8) | /* 32 kHz */
|
||||
BF_TIMROT_TIMCTRLn_PRESCALE(0) |
|
||||
BM_TIMROT_TIMCTRLn_RELOAD |
|
||||
BM_TIMROT_TIMCTRLn_UPDATE));
|
||||
|
||||
HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
|
||||
HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define stmp3xxx_suspend_timer NULL
|
||||
#define stmp3xxx_resume_timer NULL
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
struct sys_timer stmp3xxx_timer = {
|
||||
.init = stmp3xxx_init_timer,
|
||||
.suspend = stmp3xxx_suspend_timer,
|
||||
.resume = stmp3xxx_resume_timer,
|
||||
};
|
||||
Loading…
Reference in New Issue