EDAC, MCE: Complete NB MCE decoders
Add support for decoding F14h BU MCEs and improve decoding of the remaining families. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>wifi-calibration
Borislav Petkov
Borislav Petkov
parent
ded5062328
commit
5ce88f6ea6
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@ -482,7 +482,6 @@ extern const char *rrrr_msgs[16];
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extern const char *to_msgs[2];
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extern const char *pp_msgs[4];
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extern const char *ii_msgs[4];
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extern const char *ext_msgs[32];
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extern const char *htlink_msgs[8];
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#ifdef CONFIG_EDAC_DEBUG
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@ -5,6 +5,8 @@
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static struct amd_decoder_ops *fam_ops;
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static u8 nb_err_cpumask = 0xf;
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static bool report_gart_errors;
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static void (*nb_bus_decoder)(int node_id, struct mce *m, u32 nbcfg);
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@ -61,45 +63,16 @@ EXPORT_SYMBOL_GPL(to_msgs);
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const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
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EXPORT_SYMBOL_GPL(ii_msgs);
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/*
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* Map the 4 or 5 (family-specific) bits of Extended Error code to the
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* string table.
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*/
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const char *ext_msgs[] = {
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"K8 ECC error", /* 0_0000b */
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"CRC error on link", /* 0_0001b */
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"Sync error packets on link", /* 0_0010b */
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"Master Abort during link operation", /* 0_0011b */
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"Target Abort during link operation", /* 0_0100b */
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"Invalid GART PTE entry during table walk", /* 0_0101b */
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"Unsupported atomic RMW command received", /* 0_0110b */
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"WDT error: NB transaction timeout", /* 0_0111b */
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"ECC/ChipKill ECC error", /* 0_1000b */
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"SVM DEV Error", /* 0_1001b */
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"Link Data error", /* 0_1010b */
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"Link/L3/Probe Filter Protocol error", /* 0_1011b */
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"NB Internal Arrays Parity error", /* 0_1100b */
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"DRAM Address/Control Parity error", /* 0_1101b */
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"Link Transmission error", /* 0_1110b */
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"GART/DEV Table Walk Data error" /* 0_1111b */
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"Res 0x100 error", /* 1_0000b */
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"Res 0x101 error", /* 1_0001b */
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"Res 0x102 error", /* 1_0010b */
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"Res 0x103 error", /* 1_0011b */
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"Res 0x104 error", /* 1_0100b */
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"Res 0x105 error", /* 1_0101b */
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"Res 0x106 error", /* 1_0110b */
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"Res 0x107 error", /* 1_0111b */
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"Res 0x108 error", /* 1_1000b */
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"Res 0x109 error", /* 1_1001b */
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"Res 0x10A error", /* 1_1010b */
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"Res 0x10B error", /* 1_1011b */
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"ECC error in L3 Cache Data", /* 1_1100b */
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"L3 Cache Tag error", /* 1_1101b */
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"L3 Cache LRU Parity error", /* 1_1110b */
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"Probe Filter error" /* 1_1111b */
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static const char *f10h_nb_mce_desc[] = {
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"HT link data error",
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"Protocol error (link, L3, probe filter, etc.)",
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"Parity error in NB-internal arrays",
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"Link Retry due to IO link transmission error",
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"L3 ECC data cache error",
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"ECC error in L3 cache tag",
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"L3 LRU parity bits error",
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"ECC Error in the Probe Filter directory"
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};
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EXPORT_SYMBOL_GPL(ext_msgs);
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static bool f10h_dc_mce(u16 ec)
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{
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@ -366,19 +339,97 @@ wrong_ls_mce:
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pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
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}
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static bool k8_nb_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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switch (xec) {
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case 0x1:
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pr_cont("CRC error detected on HT link.\n");
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break;
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case 0x5:
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pr_cont("Invalid GART PTE entry during GART table walk.\n");
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break;
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case 0x6:
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pr_cont("Unsupported atomic RMW received from an IO link.\n");
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break;
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case 0x0:
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case 0x8:
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pr_cont("DRAM ECC error detected on the NB.\n");
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break;
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case 0xd:
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pr_cont("Parity error on the DRAM addr/ctl signals.\n");
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break;
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default:
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ret = false;
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break;
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}
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return ret;
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}
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static bool f10h_nb_mce(u16 ec, u8 xec)
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{
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bool ret = true;
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u8 offset = 0;
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if (k8_nb_mce(ec, xec))
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return true;
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switch(xec) {
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case 0xa ... 0xc:
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offset = 10;
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break;
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case 0xe:
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offset = 11;
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break;
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case 0xf:
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if (TLB_ERROR(ec))
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pr_cont("GART Table Walk data error.\n");
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else if (BUS_ERROR(ec))
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pr_cont("DMA Exclusion Vector Table Walk error.\n");
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else
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ret = false;
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goto out;
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break;
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case 0x1c ... 0x1f:
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offset = 24;
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break;
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default:
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ret = false;
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goto out;
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break;
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}
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pr_cont("%s.\n", f10h_nb_mce_desc[xec - offset]);
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out:
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return ret;
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}
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static bool f14h_nb_mce(u16 ec, u8 xec)
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{
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return false;
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}
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void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
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{
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u32 ec = m->status & 0xffff;
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u8 xec = (m->status >> 16) & 0x1f;
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u16 ec = m->status & 0xffff;
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u32 nbsh = (u32)(m->status >> 32);
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u32 nbsl = (u32)m->status;
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/*
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* GART TLB error reporting is disabled by default. Bail out early.
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*/
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if (TLB_ERROR(ec) && !report_gart_errors)
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return;
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pr_emerg(HW_ERR "Northbridge Error, node %d", node_id);
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pr_emerg(HW_ERR "Northbridge Error, node %d: ", node_id);
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/*
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* F10h, revD can disable ErrCpu[3:0] so check that first and also the
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@ -387,20 +438,50 @@ void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
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if ((boot_cpu_data.x86 == 0x10) &&
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(boot_cpu_data.x86_model > 7)) {
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if (nbsh & K8_NBSH_ERR_CPU_VAL)
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pr_cont(", core: %u\n", (u8)(nbsh & 0xf));
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pr_cont(", core: %u", (u8)(nbsh & nb_err_cpumask));
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} else {
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u8 assoc_cpus = nbsh & 0xf;
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u8 assoc_cpus = nbsh & nb_err_cpumask;
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if (assoc_cpus > 0)
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pr_cont(", core: %d", fls(assoc_cpus) - 1);
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pr_cont("\n");
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}
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pr_emerg(HW_ERR "%s.\n", EXT_ERR_MSG(nbsl));
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switch (xec) {
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case 0x2:
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pr_cont("Sync error (sync packets on HT link detected).\n");
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return;
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if (BUS_ERROR(ec) && nb_bus_decoder)
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nb_bus_decoder(node_id, m, nbcfg);
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case 0x3:
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pr_cont("HT Master abort.\n");
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return;
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case 0x4:
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pr_cont("HT Target abort.\n");
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return;
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case 0x7:
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pr_cont("NB Watchdog timeout.\n");
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return;
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case 0x9:
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pr_cont("SVM DMA Exclusion Vector error.\n");
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return;
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default:
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break;
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}
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if (!fam_ops->nb_mce(ec, xec))
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goto wrong_nb_mce;
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if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10)
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if ((xec == 0x8 || xec == 0x0) && nb_bus_decoder)
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nb_bus_decoder(node_id, m, nbcfg);
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return;
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wrong_nb_mce:
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pr_emerg(HW_ERR "Corrupted NB MCE info?\n");
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}
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EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
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@ -430,11 +511,30 @@ static inline void amd_decode_err_code(u16 ec)
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pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec);
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}
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/*
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* Filter out unwanted MCE signatures here.
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*/
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static bool amd_filter_mce(struct mce *m)
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{
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u8 xec = (m->status >> 16) & 0x1f;
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/*
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* NB GART TLB error reporting is disabled by default.
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*/
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if (m->bank == 4 && xec == 0x5 && !report_gart_errors)
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return true;
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return false;
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}
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int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
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{
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struct mce *m = (struct mce *)data;
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int node, ecc;
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if (amd_filter_mce(m))
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return NOTIFY_STOP;
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pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank);
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pr_cont("%sorrected error, other errors lost: %s, "
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@ -509,16 +609,20 @@ static int __init mce_amd_init(void)
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case 0xf:
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fam_ops->dc_mce = k8_dc_mce;
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fam_ops->ic_mce = k8_ic_mce;
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fam_ops->nb_mce = k8_nb_mce;
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break;
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case 0x10:
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fam_ops->dc_mce = f10h_dc_mce;
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fam_ops->ic_mce = k8_ic_mce;
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fam_ops->nb_mce = f10h_nb_mce;
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break;
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case 0x14:
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nb_err_cpumask = 0x3;
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fam_ops->dc_mce = f14h_dc_mce;
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fam_ops->ic_mce = f14h_ic_mce;
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fam_ops->nb_mce = f14h_nb_mce;
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break;
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default:
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@ -7,7 +7,6 @@
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#define ERROR_CODE(x) ((x) & 0xffff)
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#define EXT_ERROR_CODE(x) (((x) >> 16) & 0x1f)
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#define EXT_ERR_MSG(x) ext_msgs[EXT_ERROR_CODE(x)]
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#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
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#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
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@ -83,7 +82,6 @@ extern const char *rrrr_msgs[];
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extern const char *pp_msgs[];
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extern const char *to_msgs[];
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extern const char *ii_msgs[];
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extern const char *ext_msgs[];
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/*
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* relevant NB regs
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@ -102,6 +100,7 @@ struct err_regs {
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struct amd_decoder_ops {
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bool (*dc_mce)(u16);
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bool (*ic_mce)(u16);
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bool (*nb_mce)(u16, u8);
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};
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void amd_report_gart_errors(bool);
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