Clk:spear3xx:Fix: Rename clk ids within predefined limit
The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk ras_gen1_synth_gate_clk -> ras_syn1_gclk ras_pll3_48m -> ras_pll3_ pll3_48m -> pll3_ Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
parent
e28f1aa110
commit
5cfc545f50
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@ -87,7 +87,7 @@ void __init spear3xx_map_io(void)
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static void __init spear3xx_timer_init(void)
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{
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char pclk_name[] = "pll3_48m_clk";
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char pclk_name[] = "pll3_clk";
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struct clk *gpt_clk, *pclk;
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spear3xx_clk_init();
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@ -122,12 +122,12 @@ static struct gpt_rate_tbl gpt_rtbl[] = {
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};
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/* clock parents */
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static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
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static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
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static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
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static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk",
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};
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static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", };
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static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", };
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static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
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static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", };
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static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", };
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static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
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static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
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static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
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"pll2_clk", };
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@ -137,7 +137,7 @@ static void __init spear300_clk_init(void)
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{
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struct clk *clk;
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clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
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clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
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1, 1);
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clk_register_clkdev(clk, NULL, "60000000.clcd");
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@ -219,15 +219,11 @@ static void __init spear310_clk_init(void)
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#define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0
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#define SPEAR320_UARTX_PCLK_VAL_APB 0x1
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static const char *i2s_ref_parents[] = { "ras_pll2_clk",
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"ras_gen2_synth_gate_clk", };
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static const char *sdhci_parents[] = { "ras_pll3_48m_clk",
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"ras_gen3_synth_gate_clk",
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};
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static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
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static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
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static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
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"ras_gen0_synth_gate_clk", };
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static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk",
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};
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"ras_syn0_gclk", };
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static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
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static void __init spear320_clk_init(void)
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{
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@ -237,7 +233,7 @@ static void __init spear320_clk_init(void)
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CLK_IS_ROOT, 125000000);
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clk_register_clkdev(clk, "smii_125m_pad", NULL);
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clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
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clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
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1, 1);
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clk_register_clkdev(clk, NULL, "90000000.clcd");
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@ -363,9 +359,9 @@ void __init spear3xx_clk_init(void)
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clk_register_clkdev(clk, NULL, "fc900000.rtc");
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/* clock derived from 24 MHz osc clk */
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clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
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clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
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48000000);
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clk_register_clkdev(clk, "pll3_48m_clk", NULL);
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clk_register_clkdev(clk, "pll3_clk", NULL);
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clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
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1);
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@ -392,98 +388,98 @@ void __init spear3xx_clk_init(void)
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HCLK_RATIO_MASK, 0, &_lock);
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clk_register_clkdev(clk, "ahb_clk", NULL);
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clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
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"pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "uart_synth_clk", NULL);
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clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
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clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
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UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "uart_syn_clk", NULL);
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clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
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clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
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ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG,
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UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "uart0_mux_clk", NULL);
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clk_register_clkdev(clk, "uart0_mclk", NULL);
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clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0,
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PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock);
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clk = clk_register_gate(NULL, "uart0", "uart0_mclk", 0, PERIP1_CLK_ENB,
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UART_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d0000000.serial");
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clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
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"pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "firda_synth_clk", NULL);
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clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
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clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
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FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "firda_syn_clk", NULL);
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clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
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clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
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ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
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FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "firda_mux_clk", NULL);
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clk_register_clkdev(clk, "firda_mclk", NULL);
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clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
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clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
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PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "firda");
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/* gpt clocks */
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clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
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ARRAY_SIZE(gpt_rtbl), &_lock);
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clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
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ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG,
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GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt0");
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clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents,
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clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
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ARRAY_SIZE(gpt_rtbl), &_lock);
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clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
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ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG,
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GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
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clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
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clk_register_clkdev(clk, "gpt1_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
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PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt1");
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clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
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gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
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clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
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clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
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ARRAY_SIZE(gpt_rtbl), &_lock);
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clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
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ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
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GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
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clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
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clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
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clk_register_clkdev(clk, "gpt2_mclk", NULL);
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clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
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PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "gpt2");
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/* general synths clocks */
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clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk",
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"pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "gen0_synth_clk", NULL);
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clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL);
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clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk",
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0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "gen0_syn_clk", NULL);
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clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
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clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk",
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"pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "gen1_synth_clk", NULL);
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clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL);
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clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk",
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0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
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&_lock, &clk1);
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clk_register_clkdev(clk, "gen1_syn_clk", NULL);
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clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
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clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents,
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clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
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ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
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GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
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&_lock);
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clk_register_clkdev(clk, "gen2_3_parent_clk", NULL);
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clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
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clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk",
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"gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
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clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
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"gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "gen2_synth_clk", NULL);
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clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL);
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clk_register_clkdev(clk, "gen2_syn_clk", NULL);
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clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
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clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk",
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"gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
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clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk",
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"gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
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ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
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clk_register_clkdev(clk, "gen3_synth_clk", NULL);
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clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL);
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clk_register_clkdev(clk, "gen3_syn_clk", NULL);
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clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
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/* clock derived from pll3 clk */
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clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0,
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PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock);
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clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
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USBH_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "usbh_clk", NULL);
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clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
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@ -494,8 +490,8 @@ void __init spear3xx_clk_init(void)
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1);
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clk_register_clkdev(clk, "usbh.1_clk", NULL);
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clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
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PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
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clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
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USBD_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "designware_udc");
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/* clock derived from ahb clk */
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@ -579,29 +575,25 @@ void __init spear3xx_clk_init(void)
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RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_pll2_clk", NULL);
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clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0,
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clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
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RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL);
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clk_register_clkdev(clk, "ras_pll3_clk", NULL);
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clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk",
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"gen0_synth_gate_clk", 0, RAS_CLK_ENB,
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RAS_SYNT0_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL);
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clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", 0,
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RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
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clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk",
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"gen1_synth_gate_clk", 0, RAS_CLK_ENB,
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RAS_SYNT1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL);
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clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", 0,
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RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
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clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk",
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"gen2_synth_gate_clk", 0, RAS_CLK_ENB,
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RAS_SYNT2_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL);
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clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", 0,
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RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
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clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk",
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"gen3_synth_gate_clk", 0, RAS_CLK_ENB,
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RAS_SYNT3_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL);
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clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", 0,
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RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
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if (of_machine_is_compatible("st,spear300"))
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spear300_clk_init();
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