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[Blackfin] arch: merge ip0x-specific board changes 

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
wifi-calibration
Mike Frysinger 2008-04-24 05:03:26 +08:00 committed by Bryan Wu
parent f950f605b9
commit 5d1617b247
6 changed files with 1551 additions and 2 deletions
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5
arch/blackfin/Kconfig
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@ -249,7 +249,7 @@ config MEM_MT48LC8M32B2B5_7
config MEM_MT48LC32M16A2TG_75
bool
depends on (BFIN527_EZKIT)
depends on (BFIN527_EZKIT || BFIN532_IP0X)
default y
source "arch/blackfin/mach-bf527/Kconfig"
@ -281,6 +281,7 @@ config CLKIN_HZ
default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
default "30000000" if BFIN561_EZKIT
default "24576000" if PNAV10
default "10000000" if BFIN532_IP0X
help
The frequency of CLKIN crystal oscillator on the board in Hz.
@ -304,6 +305,7 @@ config MEM_ADD_WIDTH
default 10 if BFIN537_STAMP
default 11 if BFIN533_STAMP
default 10 if PNAV10
default 10 if BFIN532_IP0X
config PLL_BYPASS
bool "Bypass PLL"
@ -450,6 +452,7 @@ config MEM_SIZE
default 64 if PNAV10
default 32 if H8606_HVSISTEMAS
default 64 if BFIN548_BLUETECHNIX_CM
default 64 if BFIN532_IP0X
choice
prompt "DDR SDRAM Chip Type"

1252
arch/blackfin/configs/IP0X_defconfig 100644
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File diff suppressed because it is too large Load Diff

6
arch/blackfin/mach-bf533/boards/Kconfig
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@ -26,6 +26,12 @@ config H8606_HVSISTEMAS
help
HV Sistemas H8606 board support.
config BFIN532_IP0X
bool "IP04/IP08 IP-PBX"
depends on (BF532)
help
Core support for IP04/IP04 open hardware IP-PBX.
config GENERIC_BF533_BOARD
bool "Generic"
help

1
arch/blackfin/mach-bf533/boards/Makefile
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@ -4,6 +4,7 @@
obj-$(CONFIG_GENERIC_BF533_BOARD) += generic_board.o
obj-$(CONFIG_BFIN533_STAMP) += stamp.o
obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o
obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o

279
arch/blackfin/mach-bf533/boards/ip0x.c 100644
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@ -0,0 +1,279 @@
/*
* File: arch/blackfin/mach-bf533/ip0x.c
* Based on: arch/blackfin/mach-bf533/bf1.c
* Based on: arch/blackfin/mach-bf533/stamp.c
* Author: Ivan Danov <idanov@gmail.com>
* Modified for IP0X David Rowe
*
* Created: 2007
* Description: Board info file for the IP04/IP08 boards, which
* are derived from the BlackfinOne V2.0 boards.
*
* Modified:
* COpyright 2007 David Rowe
* Copyright 2006 Intratrade Ltd.
* Copyright 2005 National ICT Australia (NICTA)
* Copyright 2004-2006 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h>
#endif
#include <asm/irq.h>
#include <asm/bfin5xx_spi.h>
/*
* Name the Board for the /proc/cpuinfo
*/
const char bfin_board_name[] = "IP04/IP08";
/*
* Driver needs to know address, irq and flag pin.
*/
#if defined(CONFIG_BFIN532_IP0X)
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
#include <linux/dm9000.h>
static struct resource dm9000_resource1[] = {
{
.start = 0x20100000,
.end = 0x20100000 + 1,
.flags = IORESOURCE_MEM
},{
.start = 0x20100000 + 2,
.end = 0x20100000 + 3,
.flags = IORESOURCE_MEM
},{
.start = IRQ_PF15,
.end = IRQ_PF15,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
}
};
static struct resource dm9000_resource2[] = {
{
.start = 0x20200000,
.end = 0x20200000 + 1,
.flags = IORESOURCE_MEM
},{
.start = 0x20200000 + 2,
.end = 0x20200000 + 3,
.flags = IORESOURCE_MEM
},{
.start = IRQ_PF14,
.end = IRQ_PF14,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
}
};
/*
* for the moment we limit ourselves to 16bit IO until some
* better IO routines can be written and tested
*/
static struct dm9000_plat_data dm9000_platdata1 = {
.flags = DM9000_PLATF_16BITONLY,
};
static struct platform_device dm9000_device1 = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(dm9000_resource1),
.resource = dm9000_resource1,
.dev = {
.platform_data = &dm9000_platdata1,
}
};
static struct dm9000_plat_data dm9000_platdata2 = {
.flags = DM9000_PLATF_16BITONLY,
};
static struct platform_device dm9000_device2 = {
.name = "dm9000",
.id = 1,
.num_resources = ARRAY_SIZE(dm9000_resource2),
.resource = dm9000_resource2,
.dev = {
.platform_data = &dm9000_platdata2,
}
};
#endif
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
/*
* CPOL (Clock Polarity)
* 0 - Active high SCK
* 1 - Active low SCK
* CPHA (Clock Phase) Selects transfer format and operation mode
* 0 - SCLK toggles from middle of the first data bit, slave select
* pins controlled by hardware.
* 1 - SCLK toggles from beginning of first data bit, slave select
* pins controller by user software.
* .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
* NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
* NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
*/
.ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
.enable_dma = 0, /* if 1 - block!!! */
.bits_per_word = 8,
.cs_change_per_word = 0,
};
#endif
/* Notice: for blackfin, the speed_hz is the value of register
* SPI_BAUD, not the real baudrate */
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
{
.modalias = "spi_mmc",
.max_speed_hz = 2,
.bus_num = 1,
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
.platform_data = NULL,
.controller_data = &spi_mmc_chip_info,
},
#endif
};
/* SPI controller data */
static struct bfin5xx_spi_master spi_bfin_master_info = {
.num_chipselect = 8,
.enable_dma = 1, /* master has the ability to do dma transfer */
};
static struct platform_device spi_bfin_master_device = {
.name = "bfin-spi-master",
.id = 1, /* Bus number */
.dev = {
.platform_data = &spi_bfin_master_info, /* Passed to driver */
},
};
#endif /* spi master and devices */
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
{
.start = 0xFFC00400,
.end = 0xFFC004FF,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device bfin_uart_device = {
.name = "bfin-uart",
.id = 1,
.num_resources = ARRAY_SIZE(bfin_uart_resources),
.resource = bfin_uart_resources,
};
#endif
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
static struct resource isp1362_hcd_resources[] = {
{
.start = 0x20300000,
.end = 0x20300000 + 1,
.flags = IORESOURCE_MEM,
},{
.start = 0x20300000 + 2,
.end = 0x20300000 + 3,
.flags = IORESOURCE_MEM,
},{
.start = IRQ_PF11,
.end = IRQ_PF11,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct isp1362_platform_data isp1362_priv = {
.sel15Kres = 1,
.clknotstop = 0,
.oc_enable = 0, /* external OC */
.int_act_high = 0,
.int_edge_triggered = 0,
.remote_wakeup_connected = 0,
.no_power_switching = 1,
.power_switching_mode = 0,
};
static struct platform_device isp1362_hcd_device = {
.name = "isp1362-hcd",
.id = 0,
.dev = {
.platform_data = &isp1362_priv,
},
.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
.resource = isp1362_hcd_resources,
};
#endif
static struct platform_device *ip0x_devices[] __initdata = {
#if defined(CONFIG_BFIN532_IP0X)
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
&dm9000_device1,
&dm9000_device2,
#endif
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&spi_bfin_master_device,
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
&isp1362_hcd_device,
#endif
};
static int __init ip0x_init(void)
{
int i;
printk(KERN_INFO "%s(): registering device resources\n", __func__);
platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
int j = 1 << bfin_spi_board_info[i].chip_select;
/* set spi cs to 1 */
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
bfin_write_FIO_FLAG_S(j);
}
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#endif
return 0;
}
arch_initcall(ip0x_init);

10
include/asm-blackfin/mach-bf533/mem_init.h
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@ -29,7 +29,8 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD)
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
#if (CONFIG_SCLK_HZ > 119402985)
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
@ -118,6 +119,13 @@
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC32M16A2TG_75)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_GENERIC_BOARD)
/*SDRAM INFORMATION: Modify this for your board */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */