[BNX2]: Restructure RX ring init. code.
Factor out the common functions that will be used to initialize the normal RX rings and the page rings. Change the copybreak constant RX_COPY_THRESH to 128. This same constant will be used for the max. size of the linear SKB when pages are used. Copybreak will be turned off when pages are used. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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85833c6269
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5d5d001504
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@ -2117,15 +2117,12 @@ bnx2_init_context(struct bnx2 *bp)
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vcid_addr += (i << PHY_CTX_SHIFT);
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pcid_addr += (i << PHY_CTX_SHIFT);
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REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
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REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
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REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
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/* Zero out the context. */
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for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
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CTX_WR(bp, 0x00, offset, 0);
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REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
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REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
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CTX_WR(bp, vcid_addr, offset, 0);
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}
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}
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}
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@ -2459,10 +2456,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
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goto next_rx;
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}
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/* Since we don't have a jumbo ring, copy small packets
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* if mtu > 1500
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*/
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if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
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if (len <= bp->rx_copy_thresh) {
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struct sk_buff *new_skb;
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new_skb = netdev_alloc_skb(bp->dev, len + 2);
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@ -4172,50 +4166,57 @@ bnx2_init_tx_ring(struct bnx2 *bp)
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}
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static void
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bnx2_init_rx_ring(struct bnx2 *bp)
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bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
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int num_rings)
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{
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struct rx_bd *rxbd;
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int i;
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u16 prod, ring_prod;
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u32 val;
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struct rx_bd *rxbd;
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/* 8 for CRC and VLAN */
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bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
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/* hw alignment */
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bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
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ring_prod = prod = bp->rx_prod = 0;
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bp->rx_cons = 0;
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bp->rx_prod_bseq = 0;
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for (i = 0; i < bp->rx_max_ring; i++) {
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for (i = 0; i < num_rings; i++) {
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int j;
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rxbd = &bp->rx_desc_ring[i][0];
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rxbd = &rx_ring[i][0];
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for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
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rxbd->rx_bd_len = bp->rx_buf_use_size;
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rxbd->rx_bd_len = buf_size;
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rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
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}
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if (i == (bp->rx_max_ring - 1))
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if (i == (num_rings - 1))
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j = 0;
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else
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j = i + 1;
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rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
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rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
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0xffffffff;
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rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
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rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
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}
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}
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static void
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bnx2_init_rx_ring(struct bnx2 *bp)
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{
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int i;
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u16 prod, ring_prod;
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u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
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bp->rx_prod = 0;
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bp->rx_cons = 0;
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bp->rx_prod_bseq = 0;
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bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
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bp->rx_buf_use_size, bp->rx_max_ring);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
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val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
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val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
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val |= 0x02 << 8;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
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val = (u64) bp->rx_desc_mapping[0] >> 32;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
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val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
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ring_prod = prod = bp->rx_prod;
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for (i = 0; i < bp->rx_ring_size; i++) {
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if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
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break;
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@ -4230,26 +4231,40 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
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}
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static void
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bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
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static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
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{
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u32 num_rings, max;
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u32 max, num_rings = 1;
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bp->rx_ring_size = size;
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num_rings = 1;
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while (size > MAX_RX_DESC_CNT) {
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size -= MAX_RX_DESC_CNT;
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while (ring_size > MAX_RX_DESC_CNT) {
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ring_size -= MAX_RX_DESC_CNT;
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num_rings++;
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}
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/* round to next power of 2 */
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max = MAX_RX_RINGS;
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max = max_size;
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while ((max & num_rings) == 0)
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max >>= 1;
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if (num_rings != max)
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max <<= 1;
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bp->rx_max_ring = max;
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return max;
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}
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static void
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bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
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{
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u32 rx_size;
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/* 8 for CRC and VLAN */
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rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
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bp->rx_copy_thresh = RX_COPY_THRESH;
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bp->rx_buf_use_size = rx_size;
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/* hw alignment */
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bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
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bp->rx_ring_size = size;
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bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
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bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
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}
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@ -5795,16 +5810,8 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
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}
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static int
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bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
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bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
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{
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struct bnx2 *bp = netdev_priv(dev);
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if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
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(ering->tx_pending > MAX_TX_DESC_CNT) ||
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(ering->tx_pending <= MAX_SKB_FRAGS)) {
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return -EINVAL;
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}
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if (netif_running(bp->dev)) {
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bnx2_netif_stop(bp);
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bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
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@ -5812,8 +5819,8 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
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bnx2_free_mem(bp);
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}
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bnx2_set_rx_ring_size(bp, ering->rx_pending);
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bp->tx_ring_size = ering->tx_pending;
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bnx2_set_rx_ring_size(bp, rx);
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bp->tx_ring_size = tx;
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if (netif_running(bp->dev)) {
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int rc;
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@ -5824,10 +5831,25 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
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bnx2_init_nic(bp);
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bnx2_netif_start(bp);
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}
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return 0;
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}
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static int
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bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
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{
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struct bnx2 *bp = netdev_priv(dev);
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int rc;
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if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
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(ering->tx_pending > MAX_TX_DESC_CNT) ||
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(ering->tx_pending <= MAX_SKB_FRAGS)) {
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return -EINVAL;
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}
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rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
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return rc;
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}
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static void
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bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
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{
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return -EINVAL;
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dev->mtu = new_mtu;
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if (netif_running(dev)) {
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bnx2_netif_stop(bp);
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bnx2_init_nic(bp);
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bnx2_netif_start(bp);
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}
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return 0;
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return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
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}
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#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
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bp->mac_addr[4] = (u8) (reg >> 8);
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bp->mac_addr[5] = (u8) reg;
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bp->rx_offset = sizeof(struct l2_fhdr) + 2;
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bp->tx_ring_size = MAX_TX_DESC_CNT;
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bnx2_set_rx_ring_size(bp, 255);
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bp->rx_csum = 1;
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bp->rx_offset = sizeof(struct l2_fhdr) + 2;
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bp->tx_quick_cons_trip_int = 20;
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bp->tx_quick_cons_trip = 20;
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bp->tx_ticks_int = 80;
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@ -332,6 +332,11 @@ struct l2_fhdr {
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#define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
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#define BNX2_L2CTX_NX_BDIDX 0x00000018
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#define BNX2_L2CTX_HOST_PG_BDIDX 0x00000044
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#define BNX2_L2CTX_PG_BUF_SIZE 0x00000048
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#define BNX2_L2CTX_RBDC_KEY 0x0000004c
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#define BNX2_L2CTX_NX_PG_BDHADDR_HI 0x00000050
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#define BNX2_L2CTX_NX_PG_BDHADDR_LO 0x00000054
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/*
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* pci_config_l definition
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#define MAX_ETHERNET_PACKET_SIZE 1514
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#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
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#define RX_COPY_THRESH 92
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#define RX_COPY_THRESH 128
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#define BNX2_MISC_ENABLE_DEFAULT 0x7ffffff
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@ -6513,6 +6518,7 @@ struct bnx2 {
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u32 rx_offset;
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u32 rx_buf_use_size; /* useable size */
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u32 rx_buf_size; /* with alignment */
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u32 rx_copy_thresh;
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u32 rx_max_ring_idx;
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u32 rx_prod_bseq;
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