ARM: dts: Add clocks for dm814x ADPLL
These use the standard clock bindings and now we can make some of the fixed clocks into real clocks. Note that the clock output names may become optional as we probably want to eventually use descriptive names, or use just dynamically generated names as suggested by Tero. Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>steinar/wifi_calib_4_9_kernel
Tony Lindgren
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8a8b6eb7a8
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5d7e23a794
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@ -4,6 +4,157 @@
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* published by the Free Software Foundation.
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*/
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&pllss {
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/*
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* See TRM "2.6.10 Connected outputso DPLLS" and
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* "2.6.11 Connected Outputs of DPLLJ". Only clkout is
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* connected except for hdmi and usb.
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*/
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adpll_mpu_ck: adpll@40 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-s-clock";
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reg = <0x40 0x40>;
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clocks = <&devosc_ck &devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow", "clkinphif";
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clock-output-names = "481c5040.adpll.dcoclkldo",
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"481c5040.adpll.clkout",
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"481c5040.adpll.clkoutx2",
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"481c5040.adpll.clkouthif";
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};
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adpll_dsp_ck: adpll@80 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x80 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5080.adpll.dcoclkldo",
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"481c5080.adpll.clkout",
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"481c5080.adpll.clkoutldo";
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};
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adpll_sgx_ck: adpll@b0 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0xb0 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c50b0.adpll.dcoclkldo",
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"481c50b0.adpll.clkout",
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"481c50b0.adpll.clkoutldo";
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};
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adpll_hdvic_ck: adpll@e0 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0xe0 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c50e0.adpll.dcoclkldo",
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"481c50e0.adpll.clkout",
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"481c50e0.adpll.clkoutldo";
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};
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adpll_l3_ck: adpll@110 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x110 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5110.adpll.dcoclkldo",
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"481c5110.adpll.clkout",
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"481c5110.adpll.clkoutldo";
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};
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adpll_isp_ck: adpll@140 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x140 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5140.adpll.dcoclkldo",
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"481c5140.adpll.clkout",
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"481c5140.adpll.clkoutldo";
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};
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adpll_dss_ck: adpll@170 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x170 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5170.adpll.dcoclkldo",
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"481c5170.adpll.clkout",
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"481c5170.adpll.clkoutldo";
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};
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adpll_video0_ck: adpll@1a0 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x1a0 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c51a0.adpll.dcoclkldo",
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"481c51a0.adpll.clkout",
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"481c51a0.adpll.clkoutldo";
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};
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adpll_video1_ck: adpll@1d0 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x1d0 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c51d0.adpll.dcoclkldo",
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"481c51d0.adpll.clkout",
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"481c51d0.adpll.clkoutldo";
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};
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adpll_hdmi_ck: adpll@200 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x200 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5200.adpll.dcoclkldo",
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"481c5200.adpll.clkout",
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"481c5200.adpll.clkoutldo";
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};
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adpll_audio_ck: adpll@230 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x230 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5230.adpll.dcoclkldo",
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"481c5230.adpll.clkout",
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"481c5230.adpll.clkoutldo";
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};
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adpll_usb_ck: adpll@260 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x260 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5260.adpll.dcoclkldo",
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"481c5260.adpll.clkout",
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"481c5260.adpll.clkoutldo";
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};
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adpll_ddr_ck: adpll@290 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x290 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5290.adpll.dcoclkldo",
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"481c5290.adpll.clkout",
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"481c5290.adpll.clkoutldo";
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};
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};
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&pllss_clocks {
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timer1_fck: timer1_fck {
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#clock-cells = <0>;
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@ -23,6 +174,24 @@
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reg = <0x2e0>;
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};
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/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
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cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&adpll_video0_ck 1
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&adpll_video1_ck 1
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&adpll_audio_ck 1>;
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ti,bit-shift = <1>;
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reg = <0x2e8>;
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};
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/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
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cpsw_125mhz_gclk: cpsw_125mhz_gclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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};
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sysclk18_ck: sysclk18_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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@ -79,37 +248,6 @@
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compatible = "fixed-clock";
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clock-frequency = <1000000000>;
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};
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sysclk4_ck: sysclk4_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <222000000>;
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};
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sysclk6_ck: sysclk6_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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sysclk10_ck: sysclk10_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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};
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cpsw_125mhz_gclk: cpsw_125mhz_gclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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};
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cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <250000000>;
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};
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};
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&prcm_clocks {
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@ -138,6 +276,49 @@
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clock-div = <78125>;
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};
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/* L4_HS 220 MHz*/
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sysclk4_ck: sysclk4_ck {
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#clock-cells = <0>;
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compatible = "ti,fixed-factor-clock";
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clocks = <&adpll_l3_ck 1>;
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ti,clock-mult = <1>;
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ti,clock-div = <1>;
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};
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/* L4_FWCFG */
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sysclk5_ck: sysclk5_ck {
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#clock-cells = <0>;
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compatible = "ti,fixed-factor-clock";
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clocks = <&adpll_l3_ck 1>;
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ti,clock-mult = <1>;
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ti,clock-div = <2>;
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};
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/* L4_LS 110 MHz */
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sysclk6_ck: sysclk6_ck {
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#clock-cells = <0>;
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compatible = "ti,fixed-factor-clock";
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clocks = <&adpll_l3_ck 1>;
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ti,clock-mult = <1>;
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ti,clock-div = <2>;
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};
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sysclk8_ck: sysclk8_ck {
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#clock-cells = <0>;
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compatible = "ti,fixed-factor-clock";
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clocks = <&adpll_usb_ck 1>;
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ti,clock-mult = <1>;
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ti,clock-div = <1>;
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};
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sysclk10_ck: sysclk10_ck {
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compatible = "ti,divider-clock";
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reg = <0x324>;
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ti,max-div = <7>;
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#clock-cells = <0>;
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clocks = <&adpll_usb_ck 1>;
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};
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aud_clkin0_ck: aud_clkin0_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -6,6 +6,32 @@
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#include "dm814x-clocks.dtsi"
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/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
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&adpll_hdvic_ck {
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status = "disabled";
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};
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&adpll_l3_ck {
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status = "disabled";
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};
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&adpll_dss_ck {
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status = "disabled";
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};
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/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
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&sysclk4_ck {
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clocks = <&adpll_isp_ck 1>;
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};
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&sysclk5_ck {
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clocks = <&adpll_isp_ck 1>;
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};
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&sysclk6_ck {
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clocks = <&adpll_isp_ck 1>;
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};
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/*
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* Compared to dm814x, dra62x has different shifts and more mux options.
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* Please add the extra options for ysclk_14 and 16 if really needed.
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