s390/barrier: remove unnecessary serialization in atomics and bitops
The principles of operation states reads are in order, writes are in order, writes can be reordered after reads, but no reads can be reordered after writes. The atomic and bitops variantes for z196 use the interlocked-access facility instructions with a memory barrier before and after the instruction. Because of the memory ordering the first barrier is unnecessary and can be removed. Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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@ -36,7 +36,6 @@
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\
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typecheck(atomic_t *, ptr); \
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asm volatile( \
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__barrier \
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op_string " %0,%2,%1\n" \
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__barrier \
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: "=d" (old_val), "+Q" ((ptr)->counter) \
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@ -180,7 +179,6 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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\
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typecheck(atomic64_t *, ptr); \
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asm volatile( \
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__barrier \
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op_string " %0,%2,%1\n" \
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__barrier \
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: "=d" (old_val), "+Q" ((ptr)->counter) \
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@ -64,7 +64,6 @@
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\
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typecheck(unsigned long *, (__addr)); \
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asm volatile( \
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__barrier \
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__op_string " %0,%2,%1\n" \
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__barrier \
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: "=d" (__old), "+Q" (*(__addr)) \
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