drm/i915: Make IS_GEN macros only take dev_priv
Saves 1416 bytes of .rodata strings. v2: Add parantheses around dev_priv. (Ville Syrjala) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1476352990-2504-1-git-send-email-tvrtko.ursulin@linux.intel.com
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@ -4558,7 +4558,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
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else if (IS_VALLEYVIEW(dev_priv))
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num_levels = 1;
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else
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num_levels = ilk_wm_max_level(dev) + 1;
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num_levels = ilk_wm_max_level(dev_priv) + 1;
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drm_modeset_lock_all(dev);
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@ -4674,7 +4674,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
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else if (IS_VALLEYVIEW(dev_priv))
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num_levels = 1;
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else
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num_levels = ilk_wm_max_level(dev) + 1;
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num_levels = ilk_wm_max_level(dev_priv) + 1;
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if (len >= sizeof(tmp))
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return -EINVAL;
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@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
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if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_IBX;
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DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
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WARN_ON(!IS_GEN5(dev));
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WARN_ON(!IS_GEN5(dev_priv));
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} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
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dev_priv->pch_type = PCH_CPT;
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DRM_DEBUG_KMS("Found CougarPoint PCH\n");
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@ -860,7 +860,7 @@ static int i915_mmio_setup(struct drm_device *dev)
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int mmio_bar;
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int mmio_size;
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mmio_bar = IS_GEN2(dev) ? 1 : 0;
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mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
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/*
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* Before gen4, the registers and the GTT are behind different BARs.
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* However, from gen4 onwards, the registers and the GTT are shared
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@ -1013,7 +1013,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
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pci_set_master(pdev);
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/* overlay on gen2 is broken and can't address above 1G */
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if (IS_GEN2(dev)) {
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if (IS_GEN2(dev_priv)) {
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ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
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if (ret) {
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DRM_ERROR("failed to set DMA mask\n");
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@ -2738,14 +2738,14 @@ struct drm_i915_cmd_table {
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* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
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* chips, etc.).
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*/
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#define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
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#define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
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#define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
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#define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
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#define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
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#define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
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#define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
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#define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
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#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
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#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
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#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
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#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
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#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
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#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
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#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
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#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
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#define ENGINE_MASK(id) BIT(id)
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#define RENDER_RING ENGINE_MASK(RCS)
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@ -4375,15 +4375,15 @@ void i915_gem_init_swizzling(struct drm_device *dev)
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I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
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DISP_TILE_SURFACE_SWIZZLING);
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if (IS_GEN5(dev))
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if (IS_GEN5(dev_priv))
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return;
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I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
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if (IS_GEN6(dev))
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if (IS_GEN6(dev_priv))
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I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
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else if (IS_GEN7(dev))
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else if (IS_GEN7(dev_priv))
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I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
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else if (IS_GEN8(dev))
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else if (IS_GEN8(dev_priv))
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I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
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else
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BUG();
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@ -572,7 +572,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
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struct drm_i915_gem_relocation_entry *reloc,
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struct reloc_cache *cache)
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{
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struct drm_device *dev = obj->base.dev;
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struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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struct drm_gem_object *target_obj;
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struct drm_i915_gem_object *target_i915_obj;
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struct i915_vma *target_vma;
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@ -591,7 +591,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
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/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
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* pipe_control writes because the gpu doesn't properly redirect them
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* through the ppgtt for non_secure batchbuffers. */
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if (unlikely(IS_GEN6(dev) &&
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if (unlikely(IS_GEN6(dev_priv) &&
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reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
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ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
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PIN_GLOBAL);
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@ -504,19 +504,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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}
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}
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} else if (IS_GEN5(dev)) {
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} else if (IS_GEN5(dev_priv)) {
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/* On Ironlake whatever DRAM config, GPU always do
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* same swizzling setup.
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_9_10;
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swizzle_y = I915_BIT_6_SWIZZLE_9;
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} else if (IS_GEN2(dev)) {
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} else if (IS_GEN2(dev_priv)) {
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/* As far as we know, the 865 doesn't have these bit 6
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* swizzling issues.
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
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} else if (IS_MOBILE(dev_priv) || (IS_GEN3(dev_priv) &&
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!IS_G33(dev_priv))) {
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uint32_t dcc;
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/* On 9xx chipsets, channel interleave by the CPU is
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@ -554,7 +555,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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}
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/* check for L-shaped memory aka modified enhanced addressing */
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if (IS_GEN4(dev) &&
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if (IS_GEN4(dev_priv) &&
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!(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
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swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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@ -2060,11 +2060,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
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int ret;
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ppgtt->base.pte_encode = ggtt->base.pte_encode;
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if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
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if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv))
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ppgtt->switch_mm = gen6_mm_switch;
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else if (IS_HASWELL(dev_priv))
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ppgtt->switch_mm = hsw_mm_switch;
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else if (IS_GEN7(dev))
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else if (IS_GEN7(dev_priv))
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ppgtt->switch_mm = gen7_mm_switch;
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else
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BUG();
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@ -2161,6 +2161,8 @@ static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
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int i915_ppgtt_init_hw(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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gtt_write_workarounds(dev);
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/* In the case of execlists, PPGTT is enabled by the context descriptor
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@ -2172,9 +2174,9 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
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if (!USES_PPGTT(dev))
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return 0;
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if (IS_GEN6(dev))
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if (IS_GEN6(dev_priv))
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gen6_ppgtt_enable(dev);
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else if (IS_GEN7(dev))
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else if (IS_GEN7(dev_priv))
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gen7_ppgtt_enable(dev);
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else if (INTEL_INFO(dev)->gen >= 8)
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gen8_ppgtt_enable(dev);
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@ -215,7 +215,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
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u64 ggtt_start, ggtt_end;
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ggtt_start = I915_READ(PGTBL_CTL);
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if (IS_GEN4(dev))
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if (IS_GEN4(dev_priv))
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ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
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(ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
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else
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@ -271,7 +271,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
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* GEN3 firmware likes to smash pci bridges into the stolen
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* range. Apparently this works.
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*/
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if (r == NULL && !IS_GEN3(dev)) {
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if (r == NULL && !IS_GEN3(dev_priv)) {
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DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",
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base, base + (uint32_t)ggtt->stolen_size);
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base = 0;
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@ -72,7 +72,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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if (tiling_mode > I915_TILING_LAST)
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return false;
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if (IS_GEN2(dev) ||
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if (IS_GEN2(dev_priv) ||
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(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
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tile_width = 128;
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else
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@ -91,7 +91,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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if (stride > 8192)
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return false;
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if (IS_GEN3(dev)) {
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if (IS_GEN3(dev_priv)) {
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if (size > I830_FENCE_MAX_SIZE_VAL << 20)
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return false;
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} else {
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@ -610,7 +610,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
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err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
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}
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if (IS_GEN7(dev))
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if (IS_GEN7(dev_priv))
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err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
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for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
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@ -1430,7 +1430,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
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error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
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}
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if (IS_GEN7(dev))
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if (IS_GEN7(dev_priv))
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error->err_int = I915_READ(GEN7_ERR_INT);
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if (INTEL_INFO(dev)->gen >= 8) {
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@ -1438,7 +1438,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
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error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
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}
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if (IS_GEN6(dev)) {
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if (IS_GEN6(dev_priv)) {
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error->forcewake = I915_READ_FW(FORCEWAKE);
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error->gab_ctl = I915_READ(GAB_CTL);
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error->gfx_mode = I915_READ(GFX_MODE);
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@ -1455,7 +1455,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
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}
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/* 3: Feature specific registers */
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if (IS_GEN6(dev) || IS_GEN7(dev)) {
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if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
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error->gam_ecochk = I915_READ(GAM_ECOCHK);
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error->gac_eco = I915_READ(GAC_ECO_BITS);
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}
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@ -1471,7 +1471,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
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} else if (HAS_PCH_SPLIT(dev_priv)) {
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error->ier = I915_READ(DEIER);
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error->gtier[0] = I915_READ(GTIER);
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} else if (IS_GEN2(dev)) {
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} else if (IS_GEN2(dev_priv)) {
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error->ier = I915_READ16(IER);
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} else if (!IS_VALLEYVIEW(dev_priv)) {
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error->ier = I915_READ(IER);
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@ -3330,7 +3330,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
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I915_WRITE(HWSTAM, 0xffffffff);
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GEN5_IRQ_RESET(DE);
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if (IS_GEN7(dev))
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if (IS_GEN7(dev_priv))
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I915_WRITE(GEN7_ERR_INT, 0xffffffff);
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gen5_gt_irq_reset(dev);
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@ -3596,7 +3596,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
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}
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gt_irqs |= GT_RENDER_USER_INTERRUPT;
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if (IS_GEN5(dev)) {
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if (IS_GEN5(dev_priv)) {
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gt_irqs |= ILK_BSD_USER_INTERRUPT;
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} else {
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gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
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@ -70,7 +70,7 @@ int i915_save_state(struct drm_device *dev)
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i915_save_display(dev);
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if (IS_GEN4(dev))
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if (IS_GEN4(dev_priv))
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pci_read_config_word(pdev, GCDGMBUS,
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&dev_priv->regfile.saveGCDGMBUS);
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@ -116,7 +116,7 @@ int i915_restore_state(struct drm_device *dev)
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i915_gem_restore_fences(dev);
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if (IS_GEN4(dev))
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if (IS_GEN4(dev_priv))
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pci_write_config_word(pdev, GCDGMBUS,
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dev_priv->regfile.saveGCDGMBUS);
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i915_restore_display(dev);
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@ -259,7 +259,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
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* DAC limit supposedly 355 MHz.
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*/
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max_clock = 270000;
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else if (IS_GEN3(dev) || IS_GEN4(dev))
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else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
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max_clock = 400000;
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else
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max_clock = 350000;
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@ -567,7 +567,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
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/* Set the border color to purple. */
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I915_WRITE(bclrpat_reg, 0x500050);
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if (!IS_GEN2(dev)) {
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if (!IS_GEN2(dev_priv)) {
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uint32_t pipeconf = I915_READ(pipeconf_reg);
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I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
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POSTING_READ(pipeconf_reg);
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@ -899,7 +899,7 @@ void intel_crt_init(struct drm_device *dev)
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else
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crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
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if (IS_GEN2(dev))
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if (IS_GEN2(dev_priv))
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connector->interlace_allowed = 0;
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else
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connector->interlace_allowed = 1;
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@ -1045,7 +1045,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
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u32 line1, line2;
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u32 line_mask;
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if (IS_GEN2(dev))
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if (IS_GEN2(dev_priv))
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line_mask = DSL_LINEMASK_GEN2;
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else
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line_mask = DSL_LINEMASK_GEN3;
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@ -3945,7 +3945,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
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temp = I915_READ(reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_2;
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if (IS_GEN6(dev)) {
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if (IS_GEN6(dev_priv)) {
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temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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/* SNB-B */
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temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
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@ -4983,7 +4983,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
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* FIXME: Need to fix the logic to work when we turn off all planes
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* but leave the pipe running.
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*/
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if (IS_GEN2(dev))
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if (IS_GEN2(dev_priv))
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||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
|
||||
|
||||
/* Underruns don't always raise interrupts, so check manually. */
|
||||
|
@ -5006,7 +5006,7 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
|
|||
* FIXME: Need to fix the logic to work when we turn off all planes
|
||||
* but leave the pipe running.
|
||||
*/
|
||||
if (IS_GEN2(dev))
|
||||
if (IS_GEN2(dev_priv))
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
|
||||
|
||||
/*
|
||||
|
@ -6773,7 +6773,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
|
|||
|
||||
intel_crtc->active = true;
|
||||
|
||||
if (!IS_GEN2(dev))
|
||||
if (!IS_GEN2(dev_priv))
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
|
||||
|
||||
intel_encoders_pre_enable(crtc, pipe_config, old_state);
|
||||
|
@ -6821,7 +6821,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
|
|||
* On gen2 planes are double buffered but the pipe isn't, so we must
|
||||
* wait for planes to fully turn off before disabling the pipe.
|
||||
*/
|
||||
if (IS_GEN2(dev))
|
||||
if (IS_GEN2(dev_priv))
|
||||
intel_wait_for_vblank(dev, pipe);
|
||||
|
||||
intel_encoders_disable(crtc, old_crtc_state, old_state);
|
||||
|
@ -6846,7 +6846,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
|
|||
|
||||
intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
|
||||
|
||||
if (!IS_GEN2(dev))
|
||||
if (!IS_GEN2(dev_priv))
|
||||
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
|
||||
}
|
||||
|
||||
|
@ -9844,7 +9844,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
|
|||
/* We currently do not free assignements of panel fitters on
|
||||
* ivb/hsw (since we don't use the higher upscaling modes which
|
||||
* differentiates them) so just WARN about this case for now. */
|
||||
if (IS_GEN7(dev)) {
|
||||
if (IS_GEN7(dev_priv)) {
|
||||
WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
|
||||
PF_PIPE_SEL_IVB(crtc->pipe));
|
||||
}
|
||||
|
@ -11320,7 +11320,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
|
|||
return dev_priv->vbt.lvds_ssc_freq;
|
||||
else if (HAS_PCH_SPLIT(dev_priv))
|
||||
return 120000;
|
||||
else if (!IS_GEN2(dev))
|
||||
else if (!IS_GEN2(dev_priv))
|
||||
return 96000;
|
||||
else
|
||||
return 48000;
|
||||
|
@ -11353,7 +11353,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
|
|||
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
|
||||
}
|
||||
|
||||
if (!IS_GEN2(dev)) {
|
||||
if (!IS_GEN2(dev_priv)) {
|
||||
if (IS_PINEVIEW(dev))
|
||||
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
|
||||
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
|
||||
|
@ -11852,6 +11852,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
|
|||
struct drm_i915_gem_request *req,
|
||||
uint32_t flags)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct intel_ring *ring = req->ring;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
uint32_t plane_bit = 0;
|
||||
|
@ -11880,7 +11881,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
|
|||
* 48bits addresses, and we need a NOOP for the batch size to
|
||||
* stay even.
|
||||
*/
|
||||
if (IS_GEN8(dev))
|
||||
if (IS_GEN8(dev_priv))
|
||||
len += 2;
|
||||
}
|
||||
|
||||
|
@ -11917,7 +11918,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
|
|||
intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
|
||||
DERRMR_PIPEB_PRI_FLIP_DONE |
|
||||
DERRMR_PIPEC_PRI_FLIP_DONE));
|
||||
if (IS_GEN8(dev))
|
||||
if (IS_GEN8(dev_priv))
|
||||
intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
|
||||
MI_SRM_LRM_GLOBAL_GTT);
|
||||
else
|
||||
|
@ -11926,7 +11927,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
|
|||
intel_ring_emit_reg(ring, DERRMR);
|
||||
intel_ring_emit(ring,
|
||||
i915_ggtt_offset(req->engine->scratch) + 256);
|
||||
if (IS_GEN8(dev)) {
|
||||
if (IS_GEN8(dev_priv)) {
|
||||
intel_ring_emit(ring, 0);
|
||||
intel_ring_emit(ring, MI_NOOP);
|
||||
}
|
||||
|
@ -15320,7 +15321,7 @@ static bool has_edp_a(struct drm_device *dev)
|
|||
if ((I915_READ(DP_A) & DP_DETECTED) == 0)
|
||||
return false;
|
||||
|
||||
if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
|
||||
if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
|
@ -15522,7 +15523,7 @@ static void intel_setup_outputs(struct drm_device *dev)
|
|||
}
|
||||
|
||||
intel_dsi_init(dev);
|
||||
} else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
|
||||
} else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
|
||||
bool found = false;
|
||||
|
||||
if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
|
||||
|
@ -15556,7 +15557,7 @@ static void intel_setup_outputs(struct drm_device *dev)
|
|||
|
||||
if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
|
||||
intel_dp_init(dev, DP_D, PORT_D);
|
||||
} else if (IS_GEN2(dev))
|
||||
} else if (IS_GEN2(dev_priv))
|
||||
intel_dvo_init(dev);
|
||||
|
||||
if (SUPPORTS_TV(dev))
|
||||
|
@ -16381,10 +16382,10 @@ void intel_modeset_init(struct drm_device *dev)
|
|||
}
|
||||
}
|
||||
|
||||
if (IS_GEN2(dev)) {
|
||||
if (IS_GEN2(dev_priv)) {
|
||||
dev->mode_config.max_width = 2048;
|
||||
dev->mode_config.max_height = 2048;
|
||||
} else if (IS_GEN3(dev)) {
|
||||
} else if (IS_GEN3(dev_priv)) {
|
||||
dev->mode_config.max_width = 4096;
|
||||
dev->mode_config.max_height = 4096;
|
||||
} else {
|
||||
|
@ -16395,7 +16396,7 @@ void intel_modeset_init(struct drm_device *dev)
|
|||
if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
|
||||
dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
|
||||
dev->mode_config.cursor_height = 1023;
|
||||
} else if (IS_GEN2(dev)) {
|
||||
} else if (IS_GEN2(dev_priv)) {
|
||||
dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
|
||||
dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
|
||||
} else {
|
||||
|
@ -16916,7 +16917,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
|
|||
|
||||
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
||||
vlv_wm_get_hw_state(dev);
|
||||
else if (IS_GEN9(dev))
|
||||
else if (IS_GEN9(dev_priv))
|
||||
skl_wm_get_hw_state(dev);
|
||||
else if (HAS_PCH_SPLIT(dev_priv))
|
||||
ilk_wm_get_hw_state(dev);
|
||||
|
|
|
@ -1767,7 +1767,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
|
|||
|
||||
/* Split out the IBX/CPU vs CPT settings */
|
||||
|
||||
if (IS_GEN7(dev) && port == PORT_A) {
|
||||
if (IS_GEN7(dev_priv) && port == PORT_A) {
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
||||
intel_dp->DP |= DP_SYNC_HS_HIGH;
|
||||
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
||||
|
@ -2113,7 +2113,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
|
|||
|
||||
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
|
||||
pp = ironlake_get_pp_control(intel_dp);
|
||||
if (IS_GEN5(dev)) {
|
||||
if (IS_GEN5(dev_priv)) {
|
||||
/* ILK workaround: disable reset around power sequence */
|
||||
pp &= ~PANEL_POWER_RESET;
|
||||
I915_WRITE(pp_ctrl_reg, pp);
|
||||
|
@ -2121,7 +2121,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
|
|||
}
|
||||
|
||||
pp |= PANEL_POWER_ON;
|
||||
if (!IS_GEN5(dev))
|
||||
if (!IS_GEN5(dev_priv))
|
||||
pp |= PANEL_POWER_RESET;
|
||||
|
||||
I915_WRITE(pp_ctrl_reg, pp);
|
||||
|
@ -2130,7 +2130,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
|
|||
wait_panel_on(intel_dp);
|
||||
intel_dp->last_power_on = jiffies;
|
||||
|
||||
if (IS_GEN5(dev)) {
|
||||
if (IS_GEN5(dev_priv)) {
|
||||
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
|
||||
I915_WRITE(pp_ctrl_reg, pp);
|
||||
POSTING_READ(pp_ctrl_reg);
|
||||
|
@ -2443,7 +2443,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
|
|||
if (!(tmp & DP_PORT_EN))
|
||||
goto out;
|
||||
|
||||
if (IS_GEN7(dev) && port == PORT_A) {
|
||||
if (IS_GEN7(dev_priv) && port == PORT_A) {
|
||||
*pipe = PORT_TO_PIPE_CPT(tmp);
|
||||
} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
|
||||
enum pipe p;
|
||||
|
@ -2661,7 +2661,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
|
|||
}
|
||||
I915_WRITE(DP_TP_CTL(port), temp);
|
||||
|
||||
} else if ((IS_GEN7(dev) && port == PORT_A) ||
|
||||
} else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
|
||||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
|
||||
*DP &= ~DP_LINK_TRAIN_MASK_CPT;
|
||||
|
||||
|
@ -2990,7 +2990,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
|
|||
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
|
||||
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
||||
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
|
||||
else if (IS_GEN7(dev) && port == PORT_A)
|
||||
else if (IS_GEN7(dev_priv) && port == PORT_A)
|
||||
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
|
||||
else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
|
||||
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
|
||||
|
@ -3353,10 +3353,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
|
|||
signal_levels = chv_signal_levels(intel_dp);
|
||||
} else if (IS_VALLEYVIEW(dev_priv)) {
|
||||
signal_levels = vlv_signal_levels(intel_dp);
|
||||
} else if (IS_GEN7(dev) && port == PORT_A) {
|
||||
} else if (IS_GEN7(dev_priv) && port == PORT_A) {
|
||||
signal_levels = gen7_edp_signal_levels(train_set);
|
||||
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
|
||||
} else if (IS_GEN6(dev) && port == PORT_A) {
|
||||
} else if (IS_GEN6(dev_priv) && port == PORT_A) {
|
||||
signal_levels = gen6_edp_signal_levels(train_set);
|
||||
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
|
||||
} else {
|
||||
|
@ -3444,7 +3444,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
|
|||
|
||||
DRM_DEBUG_KMS("\n");
|
||||
|
||||
if ((IS_GEN7(dev) && port == PORT_A) ||
|
||||
if ((IS_GEN7(dev_priv) && port == PORT_A) ||
|
||||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
|
||||
DP &= ~DP_LINK_TRAIN_MASK_CPT;
|
||||
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
|
||||
|
|
|
@ -1722,7 +1722,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
|
|||
/* intel_pm.c */
|
||||
void intel_init_clock_gating(struct drm_device *dev);
|
||||
void intel_suspend_hw(struct drm_device *dev);
|
||||
int ilk_wm_max_level(const struct drm_device *dev);
|
||||
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
|
||||
void intel_update_watermarks(struct drm_crtc *crtc);
|
||||
void intel_init_pm(struct drm_device *dev);
|
||||
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
|
||||
|
|
|
@ -256,11 +256,11 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
|
|||
|
||||
if (HAS_GMCH_DISPLAY(dev_priv))
|
||||
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
|
||||
else if (IS_GEN5(dev) || IS_GEN6(dev))
|
||||
else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
|
||||
ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
|
||||
else if (IS_GEN7(dev))
|
||||
else if (IS_GEN7(dev_priv))
|
||||
ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
|
||||
else if (IS_GEN8(dev) || IS_GEN9(dev))
|
||||
else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
|
||||
broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
|
||||
|
||||
return old;
|
||||
|
|
|
@ -349,7 +349,6 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
|
|||
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
|
||||
struct drm_device *dev = &dev_priv->drm;
|
||||
struct i915_vma *vma;
|
||||
int ret;
|
||||
|
||||
|
@ -392,7 +391,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
|
|||
else
|
||||
I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
|
||||
|
||||
if (IS_GEN9(dev)) {
|
||||
if (IS_GEN9(dev_priv)) {
|
||||
/* DOP Clock Gating Enable for GuC clocks */
|
||||
I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
|
||||
I915_READ(GEN7_MISCCPCTL)));
|
||||
|
|
|
@ -1071,7 +1071,7 @@ void intel_lvds_init(struct drm_device *dev)
|
|||
intel_encoder->cloneable = 0;
|
||||
if (HAS_PCH_SPLIT(dev_priv))
|
||||
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
||||
else if (IS_GEN4(dev))
|
||||
else if (IS_GEN4(dev_priv))
|
||||
intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
|
||||
else
|
||||
intel_encoder->crtc_mask = (1 << 1);
|
||||
|
|
|
@ -1530,7 +1530,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
|
|||
|
||||
if (IS_I945GM(dev))
|
||||
wm_info = &i945_wm_info;
|
||||
else if (!IS_GEN2(dev))
|
||||
else if (!IS_GEN2(dev_priv))
|
||||
wm_info = &i915_wm_info;
|
||||
else
|
||||
wm_info = &i830_a_wm_info;
|
||||
|
@ -1540,7 +1540,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
|
|||
if (intel_crtc_active(crtc)) {
|
||||
const struct drm_display_mode *adjusted_mode;
|
||||
int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
|
||||
if (IS_GEN2(dev))
|
||||
if (IS_GEN2(dev_priv))
|
||||
cpp = 4;
|
||||
|
||||
adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
|
||||
|
@ -1554,7 +1554,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
|
|||
planea_wm = wm_info->max_wm;
|
||||
}
|
||||
|
||||
if (IS_GEN2(dev))
|
||||
if (IS_GEN2(dev_priv))
|
||||
wm_info = &i830_bc_wm_info;
|
||||
|
||||
fifo_size = dev_priv->display.get_fifo_size(dev, 1);
|
||||
|
@ -1562,7 +1562,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
|
|||
if (intel_crtc_active(crtc)) {
|
||||
const struct drm_display_mode *adjusted_mode;
|
||||
int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
|
||||
if (IS_GEN2(dev))
|
||||
if (IS_GEN2(dev_priv))
|
||||
cpp = 4;
|
||||
|
||||
adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
|
||||
|
@ -2082,10 +2082,10 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
|
|||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
|
||||
if (IS_GEN9(dev)) {
|
||||
if (IS_GEN9(dev_priv)) {
|
||||
uint32_t val;
|
||||
int ret, i;
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
|
||||
/* read the first set of memory latencies[0:3] */
|
||||
val = 0; /* data0 to be programmed to 0 for first set */
|
||||
|
@ -2184,10 +2184,11 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
|
|||
}
|
||||
}
|
||||
|
||||
static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
|
||||
static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
|
||||
uint16_t wm[5])
|
||||
{
|
||||
/* ILK sprite LP0 latency is 1300 ns */
|
||||
if (IS_GEN5(dev))
|
||||
if (IS_GEN5(dev_priv))
|
||||
wm[0] = 13;
|
||||
}
|
||||
|
||||
|
@ -2203,10 +2204,8 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
|
|||
wm[3] *= 2;
|
||||
}
|
||||
|
||||
int ilk_wm_max_level(const struct drm_device *dev)
|
||||
int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
|
||||
/* how many WM levels are we expecting */
|
||||
if (INTEL_GEN(dev_priv) >= 9)
|
||||
return 7;
|
||||
|
@ -2218,11 +2217,11 @@ int ilk_wm_max_level(const struct drm_device *dev)
|
|||
return 2;
|
||||
}
|
||||
|
||||
static void intel_print_wm_latency(struct drm_device *dev,
|
||||
static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
|
||||
const char *name,
|
||||
const uint16_t wm[8])
|
||||
{
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
|
||||
for (level = 0; level <= max_level; level++) {
|
||||
unsigned int latency = wm[level];
|
||||
|
@ -2237,7 +2236,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
|
|||
* - latencies are in us on gen9.
|
||||
* - before then, WM1+ latency values are in 0.5us units
|
||||
*/
|
||||
if (IS_GEN9(dev))
|
||||
if (IS_GEN9(dev_priv))
|
||||
latency *= 10;
|
||||
else if (level > 0)
|
||||
latency *= 5;
|
||||
|
@ -2251,7 +2250,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
|
|||
static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
|
||||
uint16_t wm[5], uint16_t min)
|
||||
{
|
||||
int level, max_level = ilk_wm_max_level(&dev_priv->drm);
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
|
||||
if (wm[0] >= min)
|
||||
return false;
|
||||
|
@ -2280,9 +2279,9 @@ static void snb_wm_latency_quirk(struct drm_device *dev)
|
|||
return;
|
||||
|
||||
DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
|
||||
intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
|
||||
intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
|
||||
intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
|
||||
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
|
||||
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
|
||||
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
|
||||
}
|
||||
|
||||
static void ilk_setup_wm_latency(struct drm_device *dev)
|
||||
|
@ -2296,14 +2295,14 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
|
|||
memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
|
||||
sizeof(dev_priv->wm.pri_latency));
|
||||
|
||||
intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
|
||||
intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
|
||||
intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
|
||||
|
||||
intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
|
||||
intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
|
||||
intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
|
||||
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
|
||||
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
|
||||
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
|
||||
|
||||
if (IS_GEN6(dev))
|
||||
if (IS_GEN6(dev_priv))
|
||||
snb_wm_latency_quirk(dev);
|
||||
}
|
||||
|
||||
|
@ -2312,7 +2311,7 @@ static void skl_setup_wm_latency(struct drm_device *dev)
|
|||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
|
||||
intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
|
||||
intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
|
||||
intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
|
||||
}
|
||||
|
||||
static bool ilk_validate_pipe_wm(struct drm_device *dev,
|
||||
|
@ -2350,7 +2349,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
|
|||
struct intel_plane_state *pristate = NULL;
|
||||
struct intel_plane_state *sprstate = NULL;
|
||||
struct intel_plane_state *curstate = NULL;
|
||||
int level, max_level = ilk_wm_max_level(dev), usable_level;
|
||||
int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
|
||||
struct ilk_wm_maximums max;
|
||||
|
||||
pipe_wm = &cstate->wm.ilk.optimal;
|
||||
|
@ -2437,7 +2436,7 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
|
|||
{
|
||||
struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
|
||||
struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(to_i915(dev));
|
||||
|
||||
/*
|
||||
* Start with the final, target watermarks, then combine with the
|
||||
|
@ -2521,7 +2520,7 @@ static void ilk_wm_merge(struct drm_device *dev,
|
|||
struct intel_pipe_wm *merged)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
int last_enabled_level = max_level;
|
||||
|
||||
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
|
||||
|
@ -2561,7 +2560,7 @@ static void ilk_wm_merge(struct drm_device *dev,
|
|||
* What we should check here is whether FBC can be
|
||||
* enabled sometime later.
|
||||
*/
|
||||
if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
|
||||
if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
|
||||
intel_fbc_is_active(dev_priv)) {
|
||||
for (level = 2; level <= max_level; level++) {
|
||||
struct intel_wm_level *wm = &merged->wm[level];
|
||||
|
@ -2661,7 +2660,7 @@ static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
|
|||
struct intel_pipe_wm *r1,
|
||||
struct intel_pipe_wm *r2)
|
||||
{
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(to_i915(dev));
|
||||
int level1 = 0, level2 = 0;
|
||||
|
||||
for (level = 1; level <= max_level; level++) {
|
||||
|
@ -3035,7 +3034,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
|
|||
continue;
|
||||
|
||||
/* Find the highest enabled wm level for this plane */
|
||||
for (level = ilk_wm_max_level(dev);
|
||||
for (level = ilk_wm_max_level(dev_priv);
|
||||
intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
|
||||
{ }
|
||||
|
||||
|
@ -3778,7 +3777,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
|
|||
{
|
||||
struct drm_device *dev = cstate->base.crtc->dev;
|
||||
const struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
int ret;
|
||||
|
||||
for (level = 0; level <= max_level; level++) {
|
||||
|
@ -3799,7 +3798,7 @@ static void skl_compute_wm_results(struct drm_device *dev,
|
|||
struct skl_wm_values *r,
|
||||
struct intel_crtc *intel_crtc)
|
||||
{
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(to_i915(dev));
|
||||
enum pipe pipe = intel_crtc->pipe;
|
||||
uint32_t temp;
|
||||
int i;
|
||||
|
@ -3868,7 +3867,7 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc,
|
|||
struct drm_crtc *crtc = &intel_crtc->base;
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
enum pipe pipe = intel_crtc->pipe;
|
||||
|
||||
for (level = 0; level <= max_level; level++) {
|
||||
|
@ -3889,7 +3888,7 @@ void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
|
|||
struct drm_crtc *crtc = &intel_crtc->base;
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
enum pipe pipe = intel_crtc->pipe;
|
||||
|
||||
for (level = 0; level <= max_level; level++) {
|
||||
|
@ -4339,7 +4338,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
|
|||
int level, i, max_level;
|
||||
uint32_t temp;
|
||||
|
||||
max_level = ilk_wm_max_level(dev);
|
||||
max_level = ilk_wm_max_level(dev_priv);
|
||||
|
||||
hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
|
||||
|
||||
|
@ -4439,7 +4438,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
|
|||
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
|
||||
active->linetime = hw->wm_linetime[pipe];
|
||||
} else {
|
||||
int level, max_level = ilk_wm_max_level(dev);
|
||||
int level, max_level = ilk_wm_max_level(dev_priv);
|
||||
|
||||
/*
|
||||
* For inactive pipes, all watermark levels
|
||||
|
@ -7742,7 +7741,7 @@ void intel_init_pm(struct drm_device *dev)
|
|||
/* For cxsr */
|
||||
if (IS_PINEVIEW(dev))
|
||||
i915_pineview_get_mem_freq(dev);
|
||||
else if (IS_GEN5(dev))
|
||||
else if (IS_GEN5(dev_priv))
|
||||
i915_ironlake_get_mem_freq(dev);
|
||||
|
||||
/* For FIFO watermark updates */
|
||||
|
@ -7753,9 +7752,9 @@ void intel_init_pm(struct drm_device *dev)
|
|||
} else if (HAS_PCH_SPLIT(dev_priv)) {
|
||||
ilk_setup_wm_latency(dev);
|
||||
|
||||
if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
|
||||
if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
|
||||
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
|
||||
(!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
|
||||
(!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
|
||||
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
|
||||
dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
|
||||
dev_priv->display.compute_intermediate_wm =
|
||||
|
@ -7791,12 +7790,12 @@ void intel_init_pm(struct drm_device *dev)
|
|||
dev_priv->display.update_wm = pineview_update_wm;
|
||||
} else if (IS_G4X(dev_priv)) {
|
||||
dev_priv->display.update_wm = g4x_update_wm;
|
||||
} else if (IS_GEN4(dev)) {
|
||||
} else if (IS_GEN4(dev_priv)) {
|
||||
dev_priv->display.update_wm = i965_update_wm;
|
||||
} else if (IS_GEN3(dev)) {
|
||||
} else if (IS_GEN3(dev_priv)) {
|
||||
dev_priv->display.update_wm = i9xx_update_wm;
|
||||
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
|
||||
} else if (IS_GEN2(dev)) {
|
||||
} else if (IS_GEN2(dev_priv)) {
|
||||
if (INTEL_INFO(dev)->num_pipes == 1) {
|
||||
dev_priv->display.update_wm = i845_update_wm;
|
||||
dev_priv->display.get_fifo_size = i845_get_fifo_size;
|
||||
|
|
|
@ -680,7 +680,7 @@ ilk_update_plane(struct drm_plane *plane,
|
|||
if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
|
||||
dvscntr |= DVS_TILED;
|
||||
|
||||
if (IS_GEN6(dev))
|
||||
if (IS_GEN6(dev_priv))
|
||||
dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
|
||||
|
||||
/* Sizes are 0 based */
|
||||
|
@ -1075,7 +1075,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
|
|||
intel_plane->update_plane = ilk_update_plane;
|
||||
intel_plane->disable_plane = ilk_disable_plane;
|
||||
|
||||
if (IS_GEN6(dev)) {
|
||||
if (IS_GEN6(dev_priv)) {
|
||||
plane_formats = snb_plane_formats;
|
||||
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
|
||||
} else {
|
||||
|
|
Loading…
Reference in a new issue