mfd: sec: Fix reg_offset for interrupt registers

reg_offset is offset of the status/mask registers. Now, since status_base
and mask_base are pointing to corresponding first registers, reg_offset
should start from 0 otheriwse regmap_add_irq_chip will fail during probe.

Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Inderpal Singh 2012-10-17 11:48:55 +05:30 committed by Samuel Ortiz
parent fee546ce8c
commit 5e393a2227

View file

@ -24,67 +24,67 @@
static struct regmap_irq s2mps11_irqs[] = { static struct regmap_irq s2mps11_irqs[] = {
[S2MPS11_IRQ_PWRONF] = { [S2MPS11_IRQ_PWRONF] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S2MPS11_IRQ_PWRONF_MASK, .mask = S2MPS11_IRQ_PWRONF_MASK,
}, },
[S2MPS11_IRQ_PWRONR] = { [S2MPS11_IRQ_PWRONR] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S2MPS11_IRQ_PWRONR_MASK, .mask = S2MPS11_IRQ_PWRONR_MASK,
}, },
[S2MPS11_IRQ_JIGONBF] = { [S2MPS11_IRQ_JIGONBF] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S2MPS11_IRQ_JIGONBF_MASK, .mask = S2MPS11_IRQ_JIGONBF_MASK,
}, },
[S2MPS11_IRQ_JIGONBR] = { [S2MPS11_IRQ_JIGONBR] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S2MPS11_IRQ_JIGONBR_MASK, .mask = S2MPS11_IRQ_JIGONBR_MASK,
}, },
[S2MPS11_IRQ_ACOKBF] = { [S2MPS11_IRQ_ACOKBF] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S2MPS11_IRQ_ACOKBF_MASK, .mask = S2MPS11_IRQ_ACOKBF_MASK,
}, },
[S2MPS11_IRQ_ACOKBR] = { [S2MPS11_IRQ_ACOKBR] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S2MPS11_IRQ_ACOKBR_MASK, .mask = S2MPS11_IRQ_ACOKBR_MASK,
}, },
[S2MPS11_IRQ_PWRON1S] = { [S2MPS11_IRQ_PWRON1S] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S2MPS11_IRQ_PWRON1S_MASK, .mask = S2MPS11_IRQ_PWRON1S_MASK,
}, },
[S2MPS11_IRQ_MRB] = { [S2MPS11_IRQ_MRB] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S2MPS11_IRQ_MRB_MASK, .mask = S2MPS11_IRQ_MRB_MASK,
}, },
[S2MPS11_IRQ_RTC60S] = { [S2MPS11_IRQ_RTC60S] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S2MPS11_IRQ_RTC60S_MASK, .mask = S2MPS11_IRQ_RTC60S_MASK,
}, },
[S2MPS11_IRQ_RTCA1] = { [S2MPS11_IRQ_RTCA1] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA1_MASK, .mask = S2MPS11_IRQ_RTCA1_MASK,
}, },
[S2MPS11_IRQ_RTCA2] = { [S2MPS11_IRQ_RTCA2] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S2MPS11_IRQ_RTCA2_MASK, .mask = S2MPS11_IRQ_RTCA2_MASK,
}, },
[S2MPS11_IRQ_SMPL] = { [S2MPS11_IRQ_SMPL] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S2MPS11_IRQ_SMPL_MASK, .mask = S2MPS11_IRQ_SMPL_MASK,
}, },
[S2MPS11_IRQ_RTC1S] = { [S2MPS11_IRQ_RTC1S] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S2MPS11_IRQ_RTC1S_MASK, .mask = S2MPS11_IRQ_RTC1S_MASK,
}, },
[S2MPS11_IRQ_WTSR] = { [S2MPS11_IRQ_WTSR] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S2MPS11_IRQ_WTSR_MASK, .mask = S2MPS11_IRQ_WTSR_MASK,
}, },
[S2MPS11_IRQ_INT120C] = { [S2MPS11_IRQ_INT120C] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S2MPS11_IRQ_INT120C_MASK, .mask = S2MPS11_IRQ_INT120C_MASK,
}, },
[S2MPS11_IRQ_INT140C] = { [S2MPS11_IRQ_INT140C] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S2MPS11_IRQ_INT140C_MASK, .mask = S2MPS11_IRQ_INT140C_MASK,
}, },
}; };
@ -92,146 +92,146 @@ static struct regmap_irq s2mps11_irqs[] = {
static struct regmap_irq s5m8767_irqs[] = { static struct regmap_irq s5m8767_irqs[] = {
[S5M8767_IRQ_PWRR] = { [S5M8767_IRQ_PWRR] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8767_IRQ_PWRR_MASK, .mask = S5M8767_IRQ_PWRR_MASK,
}, },
[S5M8767_IRQ_PWRF] = { [S5M8767_IRQ_PWRF] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8767_IRQ_PWRF_MASK, .mask = S5M8767_IRQ_PWRF_MASK,
}, },
[S5M8767_IRQ_PWR1S] = { [S5M8767_IRQ_PWR1S] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8767_IRQ_PWR1S_MASK, .mask = S5M8767_IRQ_PWR1S_MASK,
}, },
[S5M8767_IRQ_JIGR] = { [S5M8767_IRQ_JIGR] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8767_IRQ_JIGR_MASK, .mask = S5M8767_IRQ_JIGR_MASK,
}, },
[S5M8767_IRQ_JIGF] = { [S5M8767_IRQ_JIGF] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8767_IRQ_JIGF_MASK, .mask = S5M8767_IRQ_JIGF_MASK,
}, },
[S5M8767_IRQ_LOWBAT2] = { [S5M8767_IRQ_LOWBAT2] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8767_IRQ_LOWBAT2_MASK, .mask = S5M8767_IRQ_LOWBAT2_MASK,
}, },
[S5M8767_IRQ_LOWBAT1] = { [S5M8767_IRQ_LOWBAT1] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8767_IRQ_LOWBAT1_MASK, .mask = S5M8767_IRQ_LOWBAT1_MASK,
}, },
[S5M8767_IRQ_MRB] = { [S5M8767_IRQ_MRB] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S5M8767_IRQ_MRB_MASK, .mask = S5M8767_IRQ_MRB_MASK,
}, },
[S5M8767_IRQ_DVSOK2] = { [S5M8767_IRQ_DVSOK2] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S5M8767_IRQ_DVSOK2_MASK, .mask = S5M8767_IRQ_DVSOK2_MASK,
}, },
[S5M8767_IRQ_DVSOK3] = { [S5M8767_IRQ_DVSOK3] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S5M8767_IRQ_DVSOK3_MASK, .mask = S5M8767_IRQ_DVSOK3_MASK,
}, },
[S5M8767_IRQ_DVSOK4] = { [S5M8767_IRQ_DVSOK4] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S5M8767_IRQ_DVSOK4_MASK, .mask = S5M8767_IRQ_DVSOK4_MASK,
}, },
[S5M8767_IRQ_RTC60S] = { [S5M8767_IRQ_RTC60S] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8767_IRQ_RTC60S_MASK, .mask = S5M8767_IRQ_RTC60S_MASK,
}, },
[S5M8767_IRQ_RTCA1] = { [S5M8767_IRQ_RTCA1] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8767_IRQ_RTCA1_MASK, .mask = S5M8767_IRQ_RTCA1_MASK,
}, },
[S5M8767_IRQ_RTCA2] = { [S5M8767_IRQ_RTCA2] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8767_IRQ_RTCA2_MASK, .mask = S5M8767_IRQ_RTCA2_MASK,
}, },
[S5M8767_IRQ_SMPL] = { [S5M8767_IRQ_SMPL] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8767_IRQ_SMPL_MASK, .mask = S5M8767_IRQ_SMPL_MASK,
}, },
[S5M8767_IRQ_RTC1S] = { [S5M8767_IRQ_RTC1S] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8767_IRQ_RTC1S_MASK, .mask = S5M8767_IRQ_RTC1S_MASK,
}, },
[S5M8767_IRQ_WTSR] = { [S5M8767_IRQ_WTSR] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8767_IRQ_WTSR_MASK, .mask = S5M8767_IRQ_WTSR_MASK,
}, },
}; };
static struct regmap_irq s5m8763_irqs[] = { static struct regmap_irq s5m8763_irqs[] = {
[S5M8763_IRQ_DCINF] = { [S5M8763_IRQ_DCINF] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8763_IRQ_DCINF_MASK, .mask = S5M8763_IRQ_DCINF_MASK,
}, },
[S5M8763_IRQ_DCINR] = { [S5M8763_IRQ_DCINR] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8763_IRQ_DCINR_MASK, .mask = S5M8763_IRQ_DCINR_MASK,
}, },
[S5M8763_IRQ_JIGF] = { [S5M8763_IRQ_JIGF] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8763_IRQ_JIGF_MASK, .mask = S5M8763_IRQ_JIGF_MASK,
}, },
[S5M8763_IRQ_JIGR] = { [S5M8763_IRQ_JIGR] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8763_IRQ_JIGR_MASK, .mask = S5M8763_IRQ_JIGR_MASK,
}, },
[S5M8763_IRQ_PWRONF] = { [S5M8763_IRQ_PWRONF] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8763_IRQ_PWRONF_MASK, .mask = S5M8763_IRQ_PWRONF_MASK,
}, },
[S5M8763_IRQ_PWRONR] = { [S5M8763_IRQ_PWRONR] = {
.reg_offset = 1, .reg_offset = 0,
.mask = S5M8763_IRQ_PWRONR_MASK, .mask = S5M8763_IRQ_PWRONR_MASK,
}, },
[S5M8763_IRQ_WTSREVNT] = { [S5M8763_IRQ_WTSREVNT] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S5M8763_IRQ_WTSREVNT_MASK, .mask = S5M8763_IRQ_WTSREVNT_MASK,
}, },
[S5M8763_IRQ_SMPLEVNT] = { [S5M8763_IRQ_SMPLEVNT] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S5M8763_IRQ_SMPLEVNT_MASK, .mask = S5M8763_IRQ_SMPLEVNT_MASK,
}, },
[S5M8763_IRQ_ALARM1] = { [S5M8763_IRQ_ALARM1] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S5M8763_IRQ_ALARM1_MASK, .mask = S5M8763_IRQ_ALARM1_MASK,
}, },
[S5M8763_IRQ_ALARM0] = { [S5M8763_IRQ_ALARM0] = {
.reg_offset = 2, .reg_offset = 1,
.mask = S5M8763_IRQ_ALARM0_MASK, .mask = S5M8763_IRQ_ALARM0_MASK,
}, },
[S5M8763_IRQ_ONKEY1S] = { [S5M8763_IRQ_ONKEY1S] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8763_IRQ_ONKEY1S_MASK, .mask = S5M8763_IRQ_ONKEY1S_MASK,
}, },
[S5M8763_IRQ_TOPOFFR] = { [S5M8763_IRQ_TOPOFFR] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8763_IRQ_TOPOFFR_MASK, .mask = S5M8763_IRQ_TOPOFFR_MASK,
}, },
[S5M8763_IRQ_DCINOVPR] = { [S5M8763_IRQ_DCINOVPR] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8763_IRQ_DCINOVPR_MASK, .mask = S5M8763_IRQ_DCINOVPR_MASK,
}, },
[S5M8763_IRQ_CHGRSTF] = { [S5M8763_IRQ_CHGRSTF] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8763_IRQ_CHGRSTF_MASK, .mask = S5M8763_IRQ_CHGRSTF_MASK,
}, },
[S5M8763_IRQ_DONER] = { [S5M8763_IRQ_DONER] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8763_IRQ_DONER_MASK, .mask = S5M8763_IRQ_DONER_MASK,
}, },
[S5M8763_IRQ_CHGFAULT] = { [S5M8763_IRQ_CHGFAULT] = {
.reg_offset = 3, .reg_offset = 2,
.mask = S5M8763_IRQ_CHGFAULT_MASK, .mask = S5M8763_IRQ_CHGFAULT_MASK,
}, },
[S5M8763_IRQ_LOBAT1] = { [S5M8763_IRQ_LOBAT1] = {
.reg_offset = 4, .reg_offset = 3,
.mask = S5M8763_IRQ_LOBAT1_MASK, .mask = S5M8763_IRQ_LOBAT1_MASK,
}, },
[S5M8763_IRQ_LOBAT2] = { [S5M8763_IRQ_LOBAT2] = {
.reg_offset = 4, .reg_offset = 3,
.mask = S5M8763_IRQ_LOBAT2_MASK, .mask = S5M8763_IRQ_LOBAT2_MASK,
}, },
}; };