drm/i915: reindent Haswell register definitions
It's the only part of the i915_reg.h file that looks totally wrongly indented, so I assume my editor config is the correct one. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>wifi-calibration
Paulo Zanoni
Daniel Vetter
parent
602c43d34d
commit
5e49cea643
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@ -4278,198 +4278,184 @@
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#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
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/* HSW Power Wells */
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#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
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#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
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#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
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#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
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#define HSW_PWR_WELL_ENABLE (1<<31)
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#define HSW_PWR_WELL_STATE (1<<30)
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#define HSW_PWR_WELL_CTL5 0x45410
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#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
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#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
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#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
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#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
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#define HSW_PWR_WELL_ENABLE (1<<31)
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#define HSW_PWR_WELL_STATE (1<<30)
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#define HSW_PWR_WELL_CTL5 0x45410
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#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
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#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
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#define HSW_PWR_WELL_FORCE_ON (1<<19)
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#define HSW_PWR_WELL_CTL6 0x45414
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#define HSW_PWR_WELL_FORCE_ON (1<<19)
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#define HSW_PWR_WELL_CTL6 0x45414
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/* Per-pipe DDI Function Control */
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#define PIPE_DDI_FUNC_CTL_A 0x60400
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#define PIPE_DDI_FUNC_CTL_B 0x61400
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#define PIPE_DDI_FUNC_CTL_C 0x62400
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#define PIPE_DDI_FUNC_CTL_A 0x60400
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#define PIPE_DDI_FUNC_CTL_B 0x61400
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#define PIPE_DDI_FUNC_CTL_C 0x62400
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#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
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#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
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PIPE_DDI_FUNC_CTL_A, \
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PIPE_DDI_FUNC_CTL_B)
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#define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \
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PIPE_DDI_FUNC_CTL_B)
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#define PIPE_DDI_FUNC_ENABLE (1<<31)
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/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
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#define PIPE_DDI_PORT_MASK (7<<28)
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#define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
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#define PIPE_DDI_MODE_SELECT_MASK (7<<24)
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#define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
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#define PIPE_DDI_MODE_SELECT_DVI (1<<24)
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#define PIPE_DDI_PORT_MASK (7<<28)
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#define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
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#define PIPE_DDI_MODE_SELECT_MASK (7<<24)
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#define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
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#define PIPE_DDI_MODE_SELECT_DVI (1<<24)
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#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
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#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
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#define PIPE_DDI_MODE_SELECT_FDI (4<<24)
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#define PIPE_DDI_BPC_MASK (7<<20)
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#define PIPE_DDI_BPC_8 (0<<20)
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#define PIPE_DDI_BPC_10 (1<<20)
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#define PIPE_DDI_BPC_6 (2<<20)
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#define PIPE_DDI_BPC_12 (3<<20)
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#define PIPE_DDI_PVSYNC (1<<17)
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#define PIPE_DDI_PHSYNC (1<<16)
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#define PIPE_DDI_BFI_ENABLE (1<<4)
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#define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
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#define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
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#define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
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#define PIPE_DDI_MODE_SELECT_FDI (4<<24)
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#define PIPE_DDI_BPC_MASK (7<<20)
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#define PIPE_DDI_BPC_8 (0<<20)
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#define PIPE_DDI_BPC_10 (1<<20)
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#define PIPE_DDI_BPC_6 (2<<20)
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#define PIPE_DDI_BPC_12 (3<<20)
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#define PIPE_DDI_PVSYNC (1<<17)
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#define PIPE_DDI_PHSYNC (1<<16)
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#define PIPE_DDI_BFI_ENABLE (1<<4)
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#define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
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#define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
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#define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
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/* DisplayPort Transport Control */
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#define DP_TP_CTL_A 0x64040
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#define DP_TP_CTL_B 0x64140
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#define DP_TP_CTL(port) _PORT(port, \
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DP_TP_CTL_A, \
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DP_TP_CTL_B)
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#define DP_TP_CTL_ENABLE (1<<31)
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#define DP_TP_CTL_MODE_SST (0<<27)
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#define DP_TP_CTL_MODE_MST (1<<27)
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#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
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#define DP_TP_CTL_ENABLE (1<<31)
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#define DP_TP_CTL_MODE_SST (0<<27)
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#define DP_TP_CTL_MODE_MST (1<<27)
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#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
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#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
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#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
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#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
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#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
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#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
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#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
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#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
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/* DisplayPort Transport Status */
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#define DP_TP_STATUS_A 0x64044
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#define DP_TP_STATUS_B 0x64144
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#define DP_TP_STATUS(port) _PORT(port, \
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DP_TP_STATUS_A, \
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DP_TP_STATUS_B)
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#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
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#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
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/* DDI Buffer Control */
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#define DDI_BUF_CTL_A 0x64000
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#define DDI_BUF_CTL_B 0x64100
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#define DDI_BUF_CTL(port) _PORT(port, \
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DDI_BUF_CTL_A, \
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DDI_BUF_CTL_B)
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#define DDI_BUF_CTL_ENABLE (1<<31)
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#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
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#define DDI_BUF_CTL_ENABLE (1<<31)
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#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
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#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
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#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
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#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
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#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
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#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
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#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
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#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
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#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
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#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
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#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
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#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
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#define DDI_BUF_EMP_MASK (0xf<<24)
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#define DDI_BUF_IS_IDLE (1<<7)
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#define DDI_PORT_WIDTH_X1 (0<<1)
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#define DDI_PORT_WIDTH_X2 (1<<1)
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#define DDI_PORT_WIDTH_X4 (3<<1)
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#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
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#define DDI_BUF_EMP_MASK (0xf<<24)
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#define DDI_BUF_IS_IDLE (1<<7)
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#define DDI_PORT_WIDTH_X1 (0<<1)
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#define DDI_PORT_WIDTH_X2 (1<<1)
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#define DDI_PORT_WIDTH_X4 (3<<1)
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#define DDI_INIT_DISPLAY_DETECTED (1<<0)
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/* DDI Buffer Translations */
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#define DDI_BUF_TRANS_A 0x64E00
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#define DDI_BUF_TRANS_B 0x64E60
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#define DDI_BUF_TRANS(port) _PORT(port, \
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DDI_BUF_TRANS_A, \
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DDI_BUF_TRANS_B)
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#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
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/* Sideband Interface (SBI) is programmed indirectly, via
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* SBI_ADDR, which contains the register offset; and SBI_DATA,
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* which contains the payload */
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#define SBI_ADDR 0xC6000
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#define SBI_DATA 0xC6004
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#define SBI_ADDR 0xC6000
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#define SBI_DATA 0xC6004
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#define SBI_CTL_STAT 0xC6008
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#define SBI_CTL_OP_CRRD (0x6<<8)
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#define SBI_CTL_OP_CRWR (0x7<<8)
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#define SBI_RESPONSE_FAIL (0x1<<1)
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#define SBI_RESPONSE_SUCCESS (0x0<<1)
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#define SBI_BUSY (0x1<<0)
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#define SBI_READY (0x0<<0)
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#define SBI_RESPONSE_SUCCESS (0x0<<1)
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#define SBI_BUSY (0x1<<0)
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#define SBI_READY (0x0<<0)
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/* SBI offsets */
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#define SBI_SSCDIVINTPHASE6 0x0600
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#define SBI_SSCDIVINTPHASE6 0x0600
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#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
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#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
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#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
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#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
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#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
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#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
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#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
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#define SBI_SSCCTL 0x020c
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#define SBI_SSCCTL 0x020c
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#define SBI_SSCCTL6 0x060C
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#define SBI_SSCCTL_DISABLE (1<<0)
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#define SBI_SSCCTL_DISABLE (1<<0)
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#define SBI_SSCAUXDIV6 0x0610
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#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
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#define SBI_DBUFF0 0x2a00
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#define SBI_DBUFF0 0x2a00
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/* LPT PIXCLK_GATE */
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#define PIXCLK_GATE 0xC6020
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#define PIXCLK_GATE 0xC6020
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#define PIXCLK_GATE_UNGATE 1<<0
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#define PIXCLK_GATE_GATE 0<<0
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/* SPLL */
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#define SPLL_CTL 0x46020
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#define SPLL_CTL 0x46020
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#define SPLL_PLL_ENABLE (1<<31)
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#define SPLL_PLL_SCC (1<<28)
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#define SPLL_PLL_NON_SCC (2<<28)
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#define SPLL_PLL_FREQ_810MHz (0<<26)
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#define SPLL_PLL_FREQ_1350MHz (1<<26)
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#define SPLL_PLL_FREQ_810MHz (0<<26)
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#define SPLL_PLL_FREQ_1350MHz (1<<26)
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/* WRPLL */
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#define WRPLL_CTL1 0x46040
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#define WRPLL_CTL2 0x46060
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#define WRPLL_PLL_ENABLE (1<<31)
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#define WRPLL_PLL_SELECT_SSC (0x01<<28)
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#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
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#define WRPLL_CTL1 0x46040
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#define WRPLL_CTL2 0x46060
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#define WRPLL_PLL_ENABLE (1<<31)
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#define WRPLL_PLL_SELECT_SSC (0x01<<28)
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#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
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#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
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/* WRPLL divider programming */
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#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
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#define WRPLL_DIVIDER_POST(x) ((x)<<8)
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#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
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#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
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#define WRPLL_DIVIDER_POST(x) ((x)<<8)
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#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
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/* Port clock selection */
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#define PORT_CLK_SEL_A 0x46100
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#define PORT_CLK_SEL_B 0x46104
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#define PORT_CLK_SEL(port) _PORT(port, \
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PORT_CLK_SEL_A, \
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PORT_CLK_SEL_B)
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#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
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#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
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#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
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#define PORT_CLK_SEL_LCPLL_810 (2<<29)
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#define PORT_CLK_SEL_SPLL (3<<29)
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#define PORT_CLK_SEL_SPLL (3<<29)
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#define PORT_CLK_SEL_WRPLL1 (4<<29)
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#define PORT_CLK_SEL_WRPLL2 (5<<29)
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/* Pipe clock selection */
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#define PIPE_CLK_SEL_A 0x46140
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#define PIPE_CLK_SEL_B 0x46144
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#define PIPE_CLK_SEL(pipe) _PIPE(pipe, \
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PIPE_CLK_SEL_A, \
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PIPE_CLK_SEL_B)
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#define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B)
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/* For each pipe, we need to select the corresponding port clock */
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#define PIPE_CLK_SEL_DISABLED (0x0<<29)
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#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
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#define PIPE_CLK_SEL_DISABLED (0x0<<29)
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#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
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/* LCPLL Control */
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#define LCPLL_CTL 0x130040
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#define LCPLL_CTL 0x130040
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#define LCPLL_PLL_DISABLE (1<<31)
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#define LCPLL_PLL_LOCK (1<<30)
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#define LCPLL_CD_CLOCK_DISABLE (1<<25)
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#define LCPLL_CD_CLOCK_DISABLE (1<<25)
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#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
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/* Pipe WM_LINETIME - watermark line time */
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#define PIPE_WM_LINETIME_A 0x45270
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#define PIPE_WM_LINETIME_B 0x45274
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#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \
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PIPE_WM_LINETIME_A, \
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PIPE_WM_LINETIME_B)
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#define PIPE_WM_LINETIME_MASK (0x1ff)
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#define PIPE_WM_LINETIME_TIME(x) ((x))
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#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
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PIPE_WM_LINETIME_B)
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#define PIPE_WM_LINETIME_MASK (0x1ff)
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#define PIPE_WM_LINETIME_TIME(x) ((x))
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#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
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#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
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#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
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/* SFUSE_STRAP */
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#define SFUSE_STRAP 0xc2014
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#define SFUSE_STRAP 0xc2014
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#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
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#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
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#define SFUSE_STRAP_DDID_DETECTED (1<<0)
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