ARM: OMAP4: PM: Add L2X0 cache lowpower support
When MPUSS hits off-mode, L2 cache is lost. This patch adds L2X0 necessary maintenance operations and context restoration in the low power code. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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@ -37,8 +37,13 @@
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/* Secure Monitor mode APIs */
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#define OMAP4_MON_SCU_PWR_INDEX 0x108
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#define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100
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#define OMAP4_MON_L2X0_CTRL_INDEX 0x102
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#define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109
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#define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113
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/* Secure PPA(Primary Protected Application) APIs */
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#define OMAP4_PPA_L2_POR_INDEX 0x23
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#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
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#ifndef __ASSEMBLER__
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@ -49,6 +49,7 @@
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#include <asm/system.h>
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#include <asm/pgalloc.h>
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#include <asm/suspend.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <plat/omap44xx.h>
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@ -63,10 +64,12 @@ struct omap4_cpu_pm_info {
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struct powerdomain *pwrdm;
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void __iomem *scu_sar_addr;
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void __iomem *wkup_sar_addr;
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void __iomem *l2x0_sar_addr;
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};
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static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
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static struct powerdomain *mpuss_pd;
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static void __iomem *sar_base;
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/*
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* Program the wakeup routine address for the CPU0 and CPU1
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@ -135,6 +138,36 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
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__raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
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}
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/*
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* Store the CPU cluster state for L2X0 low power operations.
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*/
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static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
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{
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struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
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__raw_writel(save_state, pm_info->l2x0_sar_addr);
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}
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/*
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* Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
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* in every restore MPUSS OFF path.
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*/
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#ifdef CONFIG_CACHE_L2X0
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static void save_l2x0_context(void)
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{
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u32 val;
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void __iomem *l2x0_base = omap4_get_l2cache_base();
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val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
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__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
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val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
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__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
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}
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#else
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static void save_l2x0_context(void)
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{}
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#endif
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/**
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* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
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* The purpose of this function is to manage low power programming
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@ -182,6 +215,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
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set_cpu_next_pwrst(cpu, power_state);
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set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
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scu_pwrst_prepare(cpu, power_state);
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l2x0_pwrst_prepare(cpu, save_state);
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/*
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* Call low level function with targeted low power state.
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@ -239,17 +273,19 @@ int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
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int __init omap4_mpuss_init(void)
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{
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struct omap4_cpu_pm_info *pm_info;
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void __iomem *sar_base = omap4_get_sar_ram_base();
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
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return -ENODEV;
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}
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sar_base = omap4_get_sar_ram_base();
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/* Initilaise per CPU PM information */
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pm_info = &per_cpu(omap4_pm_info, 0x0);
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pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
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pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
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pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
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pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
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if (!pm_info->pwrdm) {
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pr_err("Lookup failed for CPU0 pwrdm\n");
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@ -265,6 +301,7 @@ int __init omap4_mpuss_init(void)
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pm_info = &per_cpu(omap4_pm_info, 0x1);
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pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
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pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
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pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
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pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
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if (!pm_info->pwrdm) {
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pr_err("Lookup failed for CPU1 pwrdm\n");
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@ -290,6 +327,8 @@ int __init omap4_mpuss_init(void)
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else
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__raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
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save_l2x0_context();
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return 0;
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}
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@ -23,6 +23,10 @@
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#define SCU_OFFSET0 0xd00
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#define SCU_OFFSET1 0xd04
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#define OMAP_TYPE_OFFSET 0xd10
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#define L2X0_SAVE_OFFSET0 0xd14
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#define L2X0_SAVE_OFFSET1 0xd18
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#define L2X0_AUXCTRL_OFFSET 0xd1c
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#define L2X0_PREFETCH_CTRL_OFFSET 0xd20
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/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
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#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
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@ -32,6 +32,9 @@
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ppa_zero_params:
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.word 0x0
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ppa_por_params:
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.word 1, 0
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/*
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* =============================
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* == CPU suspend finisher ==
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@ -132,6 +135,54 @@ skip_scu_gp_set:
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mcrne p15, 0, r0, c1, c0, 1
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isb
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dsb
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#ifdef CONFIG_CACHE_L2X0
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/*
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* Clean and invalidate the L2 cache.
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* Common cache-l2x0.c functions can't be used here since it
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* uses spinlocks. We are out of coherency here with data cache
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* disabled. The spinlock implementation uses exclusive load/store
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* instruction which can fail without data cache being enabled.
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* OMAP4 hardware doesn't support exclusive monitor which can
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* overcome exclusive access issue. Because of this, CPU can
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* lead to deadlock.
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*/
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bl omap4_get_sar_ram_base
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mov r8, r0
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mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
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ands r5, r5, #0x0f
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ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
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ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory.
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cmp r0, #3
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bne do_WFI
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#ifdef CONFIG_PL310_ERRATA_727915
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mov r0, #0x03
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mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
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DO_SMC
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#endif
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bl omap4_get_l2cache_base
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mov r2, r0
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ldr r0, =0xffff
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str r0, [r2, #L2X0_CLEAN_INV_WAY]
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wait:
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ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
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ldr r1, =0xffff
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ands r0, r0, r1
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bne wait
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#ifdef CONFIG_PL310_ERRATA_727915
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mov r0, #0x00
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mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
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DO_SMC
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#endif
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l2x_sync:
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bl omap4_get_l2cache_base
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mov r2, r0
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mov r0, #0x0
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str r0, [r2, #L2X0_CACHE_SYNC]
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sync:
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ldr r0, [r2, #L2X0_CACHE_SYNC]
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ands r0, r0, #0x1
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bne sync
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#endif
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do_WFI:
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bl omap_do_wfi
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@ -225,6 +276,50 @@ enable_smp_bit:
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mcreq p15, 0, r0, c1, c0, 1
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isb
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skip_ns_smp_enable:
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#ifdef CONFIG_CACHE_L2X0
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/*
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* Restore the L2 AUXCTRL and enable the L2 cache.
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* OMAP4_MON_L2X0_AUXCTRL_INDEX = Program the L2X0 AUXCTRL
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* OMAP4_MON_L2X0_CTRL_INDEX = Enable the L2 using L2X0 CTRL
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* register r0 contains value to be programmed.
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* L2 cache is already invalidate by ROM code as part
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* of MPUSS OFF wakeup path.
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*/
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ldr r2, =OMAP44XX_L2CACHE_BASE
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ldr r0, [r2, #L2X0_CTRL]
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and r0, #0x0f
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cmp r0, #1
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beq skip_l2en @ Skip if already enabled
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ldr r3, =OMAP44XX_SAR_RAM_BASE
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ldr r1, [r3, #OMAP_TYPE_OFFSET]
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cmp r1, #0x1 @ Check for HS device
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bne set_gp_por
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ldr r0, =OMAP4_PPA_L2_POR_INDEX
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ldr r1, =OMAP44XX_SAR_RAM_BASE
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ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
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adr r3, ppa_por_params
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str r4, [r3, #0x04]
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mov r1, #0x0 @ Process ID
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mov r2, #0x4 @ Flag
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mov r6, #0xff
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mov r12, #0x00 @ Secure Service ID
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DO_SMC
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b set_aux_ctrl
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set_gp_por:
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ldr r1, =OMAP44XX_SAR_RAM_BASE
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ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
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ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
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DO_SMC
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set_aux_ctrl:
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ldr r1, =OMAP44XX_SAR_RAM_BASE
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ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
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ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
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DO_SMC
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mov r0, #0x1
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ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
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DO_SMC
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skip_l2en:
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#endif
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b cpu_resume @ Jump to generic resume
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ENDPROC(omap4_cpu_resume)
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