Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Daniel writes: A few fixes, nothing shocking: - More Haswell pci ids. Includes a pile of marketing spare ids (which despite the spare moniker show up all over the place). - Fix a regression in handling modeset failures, resulting in black screens on 3 pipe setups when we've run out of pch plls (Chris). - Fix up the setcrtc semantics to unconditionally enable the outputs. Juding from git digging that has (kinda) always been the case and neatly fixes a few long-standing (i.e. forever) bug reports (Imre). - jiffies_timeout + 1 patches from Imre. They partially fix spurious wait_event failures in the interrupt-driven dp aux/i2c code. The other part is a core patch for the wait_event macros going in through -mm. A few patches more than strictly required since Imre is pushing for a general solution in 3.11. * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: avoid premature DP AUX timeouts drm/i915: avoid premature timeouts in __wait_seqno() drm/i915: use msecs_to_jiffies_timeout instead of open coding the same drm/i915: add msecs_to_jiffies_timeout to guarantee minimum duration drm/i915: force full modeset if the connector is in DPMS OFF mode drm/i915: Propagate errors back from fb set-base drm/i915: Adding more reserved PCI IDs for Haswell.
This commit is contained in:
commit
5ed77662ad
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@ -364,40 +364,64 @@ static const struct pci_device_id pciidlist[] = { /* aka */
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INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
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INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
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INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
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INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
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INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
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INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
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INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
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INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
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INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
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INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
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INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
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INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
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INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
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INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
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INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
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INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
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INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
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INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
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INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
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INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
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INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
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INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
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INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
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INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
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INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
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INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
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INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
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INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
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INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
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INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
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INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
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INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
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INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
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INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
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INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
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INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
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INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
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INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
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INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
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INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
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INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
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INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
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INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
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INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
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INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
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INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
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INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
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INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
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INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
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INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
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INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
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INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
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INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
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INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
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INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
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INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
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INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
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INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
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INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
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INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
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INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
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INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
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INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
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INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
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INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
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INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
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INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
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INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
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INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
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INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
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INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
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@ -1943,4 +1943,19 @@ static inline void __user *to_user_ptr(u64 address)
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return (void __user *)(uintptr_t)address;
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}
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static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
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{
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unsigned long j = msecs_to_jiffies(m);
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return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
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}
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static inline unsigned long
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timespec_to_jiffies_timeout(const struct timespec *value)
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{
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unsigned long j = timespec_to_jiffies(value);
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return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
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}
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#endif
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@ -1003,7 +1003,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
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wait_forever = false;
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}
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timeout_jiffies = timespec_to_jiffies(&wait_time);
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timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
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if (WARN_ON(!ring->irq_get(ring)))
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return -ENODEV;
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@ -8140,6 +8140,21 @@ static void intel_set_config_restore_state(struct drm_device *dev,
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}
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}
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static bool
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is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
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int num_connectors)
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{
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int i;
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for (i = 0; i < num_connectors; i++)
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if (connectors[i].encoder &&
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connectors[i].encoder->crtc == crtc &&
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connectors[i].dpms != DRM_MODE_DPMS_ON)
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return true;
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return false;
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}
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static void
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intel_set_config_compute_mode_changes(struct drm_mode_set *set,
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struct intel_set_config *config)
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/* We should be able to check here if the fb has the same properties
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* and then just flip_or_move it */
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if (set->crtc->fb != set->fb) {
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if (set->connectors != NULL &&
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is_crtc_connector_off(set->crtc, *set->connectors,
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set->num_connectors)) {
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config->mode_changed = true;
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} else if (set->crtc->fb != set->fb) {
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/* If we have no fb then treat it as a full mode set */
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if (set->crtc->fb == NULL) {
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DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
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@ -8157,8 +8176,9 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set,
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} else if (set->fb->pixel_format !=
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set->crtc->fb->pixel_format) {
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config->mode_changed = true;
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} else
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} else {
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config->fb_changed = true;
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}
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}
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if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
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@ -8332,11 +8352,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
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ret = intel_set_mode(set->crtc, set->mode,
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set->x, set->y, set->fb);
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if (ret) {
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DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
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set->crtc->base.id, ret);
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goto fail;
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}
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} else if (config->fb_changed) {
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intel_crtc_wait_for_pending_flips(set->crtc);
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@ -8344,18 +8359,18 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
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set->x, set->y, set->fb);
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}
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intel_set_config_free(config);
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return 0;
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if (ret) {
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DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
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set->crtc->base.id, ret);
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fail:
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intel_set_config_restore_state(dev, config);
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intel_set_config_restore_state(dev, config);
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/* Try to restore the config */
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if (config->mode_changed &&
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intel_set_mode(save_set.crtc, save_set.mode,
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save_set.x, save_set.y, save_set.fb))
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DRM_ERROR("failed to restore config after modeset failure\n");
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/* Try to restore the config */
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if (config->mode_changed &&
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intel_set_mode(save_set.crtc, save_set.mode,
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save_set.x, save_set.y, save_set.fb))
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DRM_ERROR("failed to restore config after modeset failure\n");
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}
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out_config:
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intel_set_config_free(config);
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@ -303,7 +303,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
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#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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if (has_aux_irq)
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done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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msecs_to_jiffies(10));
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msecs_to_jiffies_timeout(10));
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else
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done = wait_for_atomic(C, 10) == 0;
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if (!done)
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@ -228,7 +228,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
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* need to wake up periodically and check that ourselves. */
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I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
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for (i = 0; i < msecs_to_jiffies(50) + 1; i++) {
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for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
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prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
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TASK_UNINTERRUPTIBLE);
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@ -263,7 +263,8 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
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/* Important: The hw handles only the first bit, so set only one! */
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I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
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ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
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ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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msecs_to_jiffies_timeout(10));
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I915_WRITE(GMBUS4 + reg_offset, 0);
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