drm/nve0-/gr: some new gpc registers can have multiple copies

GK110 exposes more than one, and needs to be dealt with in the ctxsw ucode just like the TPC sets are. Broadcast is at +0xe00. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 14:32:42 +10:00 · 2013-07-01 14:32:42 +10:00 · 5ee86c4190
parent c03ff9e8fa
commit 5ee86c4190
4 changed files with 227 additions and 180 deletions
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
@ -38,6 +38,13 @@ tpc_mask:		.b32 0
 tpc_mmio_list_head:	.b32 0
 tpc_mmio_list_tail:	.b32 0

+#ifdef NVGK
+unk_count:		.b32 1
+unk_mask:		.b32 1
+unk_mmio_list_head:	.b32 #nve4_unk_mmio_head
+unk_mmio_list_tail:	.b32 #nve4_unk_mmio_tail
+#endif
+
 cmd_queue:		queue_init
 #endif

@ -160,6 +167,17 @@ init:
 	add b32 $r2 $r14
 	add b32 $r3 $r14

+#ifdef NVGK
+	// calculate per-UNK mmio context size
+	ld b32 $r14 D[$r0 + #unk_mmio_list_head]
+	ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
+	call #mmctx_size
+	ld b32 $r14 D[$r0 + #unk_count]
+	mulu $r14 $r15
+	add b32 $r2 $r14
+	add b32 $r3 $r14
+#endif
+
 	// round up base/size to 256 byte boundary (for strand SWBASE)
 	add b32 $r4 0x1300
 	shr b32 $r3 2
@ -335,7 +353,6 @@ ctx_xfer:

 	// per-TPC mmio context
 	xbit $r10 $flags $p1	// direction
-	or $r10 4		// last
 	mov $r11 0x4000
 	sethi $r11 0x500000	// base = NV_PGRAPH_GPC0_TPC0
 	ld b32 $r12 D[$r0 + #gpc_id]
@ -347,6 +364,22 @@ ctx_xfer:
 	mov $r14 0x800		// stride = 0x800
 	call #mmctx_xfer

+#ifdef NVGK
+	// per-UNK mmio context
+	xbit $r10 $flags $p1	// direction
+	or $r10 4		// last
+	mov $r11 0x3000
+	sethi $r11 0x500000	// base = NV_PGRAPH_GPC0_UNK0
+	ld b32 $r12 D[$r0 + #gpc_id]
+	shl b32 $r12 15
+	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_UNK0
+	ld b32 $r12 D[$r0 + #unk_mmio_list_head]
+	ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
+	ld b32 $r15 D[$r0 + #unk_mask]
+	mov $r14 0x200		// stride = 0x200
+	call #mmctx_xfer
+#endif
+
 	// wait for strands to finish
 	call #strand_wait

--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@ -496,26 +496,26 @@ uint32_t nvc0_grgpc_code[] = {
 	0xf0020d98,
 	0x21f500e7,
 	0xacf0015c,
-	0x04a5f001,
-	0x4000b7f1,
-	0x9850b3f0,
-	0xc4b6000c,
-	0x00bcbb0f,
-	0x98050c98,
-	0x0f98060d,
-	0x00e7f104,
-	0x5c21f508,
-	0x0721f501,
-	0x0601f402,
-/* 0x054b: ctx_xfer_post */
-	0xf11412f4,
-	0xf04afc17,
-	0x27f00213,
-	0x0012d00d,
-	0x020721f5,
-/* 0x055c: ctx_xfer_done */
-	0x048f21f5,
-	0x000000f8,
+	0x00b7f101,
+	0x50b3f040,
+	0xb6000c98,
+	0xbcbb0fc4,
+	0x050c9800,
+	0x98060d98,
+	0xe7f1040f,
+	0x21f50800,
+	0x21f5015c,
+	0x01f40207,
+	0x1412f406,
+/* 0x0548: ctx_xfer_post */
+	0x4afc17f1,
+	0xf00213f0,
+	0x12d00d27,
+	0x0721f500,
+/* 0x0559: ctx_xfer_done */
+	0x8f21f502,
+	0x0000f804,
+	0x00000000,
 	0x00000000,
 	0x00000000,
 	0x00000000,
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
@ -82,12 +82,6 @@ mmctx_data(0x000c80, 1)
 mmctx_data(0x000c8c, 1)
 mmctx_data(0x001000, 3)
 mmctx_data(0x001014, 1)
-mmctx_data(0x003024, 1)
-mmctx_data(0x0030c0, 2)
-mmctx_data(0x0030e4, 1)
-mmctx_data(0x003100, 6)
-mmctx_data(0x0031d0, 1)
-mmctx_data(0x0031e0, 2)
 nve4_gpc_mmio_tail:

 nvf0_gpc_mmio_head:
@ -166,6 +160,16 @@ mmctx_data(0x000758, 1)
 mmctx_data(0x000770, 1)
 mmctx_data(0x000778, 2)
 nvf0_tpc_mmio_tail:
+
+// UNK mmio lists
+nve4_unk_mmio_head:
+mmctx_data(0x000024, 1)
+mmctx_data(0x0000c0, 2)
+mmctx_data(0x0000e4, 1)
+mmctx_data(0x000100, 6)
+mmctx_data(0x0001d0, 1)
+mmctx_data(0x0001e0, 2)
+nve4_unk_mmio_tail:
 #undef INCLUDE_DATA

 .section #nve0_grgpc_code
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
@ -13,7 +13,15 @@ uint32_t nve0_grgpc_data[] = {
 	0x00000000,
 /* 0x0018: tpc_mmio_list_tail */
 	0x00000000,
-/* 0x001c: cmd_queue */
+/* 0x001c: unk_count */
+	0x00000001,
+/* 0x0020: unk_mask */
+	0x00000001,
+/* 0x0024: unk_mmio_list_head */
+	0x00000220,
+/* 0x0028: unk_mmio_list_tail */
+	0x00000238,
+/* 0x002c: cmd_queue */
 	0x00000000,
 	0x00000000,
 	0x00000000,
@ -32,21 +40,21 @@ uint32_t nve0_grgpc_data[] = {
 	0x00000000,
 	0x00000000,
 	0x00000000,
-/* 0x0064: chipsets */
+/* 0x0074: chipsets */
 	0x000000e4,
-	0x011c0098,
-	0x01d8018c,
+	0x011400a8,
+	0x01d00184,
 	0x000000e7,
-	0x011c0098,
-	0x01d8018c,
+	0x011400a8,
+	0x01d00184,
 	0x000000e6,
-	0x011c0098,
-	0x01d8018c,
+	0x011400a8,
+	0x01d00184,
 	0x000000f0,
-	0x018c011c,
-	0x022801d8,
+	0x01840114,
+	0x022001d0,
 	0x00000000,
-/* 0x0098: nve4_gpc_mmio_head */
+/* 0x00a8: nve4_gpc_mmio_head */
 	0x00000380,
 	0x04000400,
 	0x0800040c,
@ -74,14 +82,8 @@ uint32_t nve0_grgpc_data[] = {
 	0x00000c8c,
 	0x08001000,
 	0x00001014,
-	0x00003024,
-	0x040030c0,
-	0x000030e4,
-	0x14003100,
-	0x000031d0,
-	0x040031e0,
-/* 0x011c: nve4_gpc_mmio_tail */
-/* 0x011c: nvf0_gpc_mmio_head */
+/* 0x0114: nve4_gpc_mmio_tail */
+/* 0x0114: nvf0_gpc_mmio_head */
 	0x00000380,
 	0x04000400,
 	0x0800040c,
@ -110,8 +112,8 @@ uint32_t nve0_grgpc_data[] = {
 	0x00000d24,
 	0x08001000,
 	0x00001014,
-/* 0x018c: nvf0_gpc_mmio_tail */
-/* 0x018c: nve4_tpc_mmio_head */
+/* 0x0184: nvf0_gpc_mmio_tail */
+/* 0x0184: nve4_tpc_mmio_head */
 	0x00000048,
 	0x00000064,
 	0x00000088,
@ -131,8 +133,8 @@ uint32_t nve0_grgpc_data[] = {
 	0x00000758,
 	0x00000770,
 	0x04000778,
-/* 0x01d8: nve4_tpc_mmio_tail */
-/* 0x01d8: nvf0_tpc_mmio_head */
+/* 0x01d0: nve4_tpc_mmio_tail */
+/* 0x01d0: nvf0_tpc_mmio_head */
 	0x00000048,
 	0x00000064,
 	0x00000088,
@ -153,6 +155,14 @@ uint32_t nve0_grgpc_data[] = {
 	0x00000758,
 	0x00000770,
 	0x04000778,
+/* 0x0220: nvf0_tpc_mmio_tail */
+/* 0x0220: nve4_unk_mmio_head */
+	0x00000024,
+	0x040000c0,
+	0x000000e4,
+	0x14000100,
+	0x000001d0,
+	0x040001e0,
 };

 uint32_t nve0_grgpc_code[] = {
@ -386,7 +396,7 @@ uint32_t nve0_grgpc_code[] = {
 	0xf10004fe,
 	0xf0120017,
 	0x12d00227,
-	0x3e17f100,
+	0x5417f100,
 	0x0010fe04,
 	0x040017f1,
 	0xf0c010d0,
@ -405,7 +415,7 @@ uint32_t nve0_grgpc_code[] = {
 	0x24b60800,
 	0x0022cf06,
 /* 0x035f: init_find_chipset */
-	0xb65817f0,
+	0xb66817f0,
 	0x13980c10,
 	0x0432b800,
 	0xb00b0bf4,
@ -432,135 +442,135 @@ uint32_t nve0_grgpc_code[] = {
 	0x030e9801,
 	0xbb00effd,
 	0x3ebb002e,
-	0x0040b700,
-	0x0235b613,
-	0xb60043d0,
-	0x35b60825,
-	0x0120b606,
-	0xb60130b6,
-	0x34b60824,
-	0x022fb908,
-	0x026321f5,
-	0xf1003fbb,
-	0xb6080017,
-	0x13d00614,
-	0x0010b740,
-	0xf024bd08,
-	0x12d01f29,
-/* 0x0401: main */
-	0x0031f400,
-	0xf00028f4,
-	0x21f41cd7,
-	0xf401f439,
-	0xf404e4b0,
-	0x81fe1e18,
-	0x0627f001,
-	0x12fd20bd,
-	0x01e4b604,
-	0xfe051efd,
-	0x21f50018,
-	0x0ef404c3,
-/* 0x0431: main_not_ctx_xfer */
-	0x10ef94d3,
-	0xf501f5f0,
-	0xf402ec21,
-/* 0x043e: ih */
-	0x80f9c60e,
-	0xf90188fe,
-	0xf990f980,
-	0xf9b0f9a0,
-	0xf9e0f9d0,
-	0x800acff0,
-	0xf404abc4,
-	0xb7f11d0b,
-	0xd7f01900,
-	0x40becf1c,
-	0xf400bfcf,
-	0xb0b70421,
-	0xe7f00400,
-	0x00bed001,
-/* 0x0474: ih_no_fifo */
-	0xfc400ad0,
-	0xfce0fcf0,
-	0xfcb0fcd0,
-	0xfc90fca0,
-	0x0088fe80,
-	0x32f480fc,
-/* 0x048f: hub_barrier_done */
-	0xf001f800,
-	0x0e9801f7,
-	0x04febb00,
-	0x9418e7f1,
-	0xf440e3f0,
-	0x00f88d21,
-/* 0x04a4: ctx_redswitch */
-	0x0614e7f1,
-	0xf006e4b6,
-	0xefd020f7,
-	0x08f7f000,
-/* 0x04b4: ctx_redswitch_delay */
-	0xf401f2b6,
-	0xf7f1fd1b,
-	0xefd00a20,
-/* 0x04c3: ctx_xfer */
-	0xf100f800,
-	0xb60a0417,
-	0x1fd00614,
-	0x0711f400,
-	0x04a421f5,
-/* 0x04d4: ctx_xfer_not_load */
-	0x4afc17f1,
-	0xf00213f0,
-	0x12d00c27,
-	0x0721f500,
-	0xfc27f102,
-	0x0223f047,
-	0xf00020d0,
-	0x20b6012c,
-	0x0012d003,
+	0x090e9800,
+	0xf50a0f98,
+	0x98013d21,
+	0xeffd070e,
+	0x002ebb00,
+	0xb7003ebb,
+	0xb6130040,
+	0x43d00235,
+	0x0825b600,
+	0xb60635b6,
+	0x30b60120,
+	0x0824b601,
+	0xb90834b6,
+	0x21f5022f,
+	0x3fbb0263,
+	0x0017f100,
+	0x0614b608,
+	0xb74013d0,
+	0xbd080010,
+	0x1f29f024,
+/* 0x0417: main */
+	0xf40012d0,
+	0x28f40031,
+	0x2cd7f000,
+	0xf43921f4,
+	0xe4b0f401,
+	0x1e18f404,
+	0xf00181fe,
+	0x20bd0627,
+	0xb60412fd,
+	0x1efd01e4,
+	0x0018fe05,
+	0x04d921f5,
+/* 0x0447: main_not_ctx_xfer */
+	0x94d30ef4,
+	0xf5f010ef,
+	0xec21f501,
+	0xc60ef402,
+/* 0x0454: ih */
+	0x88fe80f9,
+	0xf980f901,
+	0xf9a0f990,
+	0xf9d0f9b0,
+	0xcff0f9e0,
+	0xabc4800a,
+	0x1d0bf404,
+	0x1900b7f1,
+	0xcf2cd7f0,
+	0xbfcf40be,
+	0x0421f400,
+	0x0400b0b7,
+	0xd001e7f0,
+/* 0x048a: ih_no_fifo */
+	0x0ad000be,
+	0xfcf0fc40,
+	0xfcd0fce0,
+	0xfca0fcb0,
+	0xfe80fc90,
+	0x80fc0088,
+	0xf80032f4,
+/* 0x04a5: hub_barrier_done */
+	0x01f7f001,
+	0xbb000e98,
+	0xe7f104fe,
+	0xe3f09418,
+	0x8d21f440,
+/* 0x04ba: ctx_redswitch */
+	0xe7f100f8,
+	0xe4b60614,
+	0x20f7f006,
+	0xf000efd0,
+/* 0x04ca: ctx_redswitch_delay */
+	0xf2b608f7,
+	0xfd1bf401,
+	0x0a20f7f1,
+	0xf800efd0,
+/* 0x04d9: ctx_xfer */
+	0x0417f100,
+	0x0614b60a,
+	0xf4001fd0,
+	0x21f50711,
+/* 0x04ea: ctx_xfer_not_load */
+	0x17f104ba,
+	0x13f04afc,
+	0x0c27f002,
+	0xf50012d0,
+	0xf1020721,
+	0xf047fc27,
+	0x20d00223,
+	0x012cf000,
+	0xd00320b6,
+	0xacf00012,
+	0x02a5f001,
+	0xf000b7f0,
+	0x0c9850b3,
+	0x0fc4b600,
+	0x9800bcbb,
+	0x0d98010c,
+	0x00e7f002,
+	0x015c21f5,
+	0xf101acf0,
+	0xf04000b7,
+	0x0c9850b3,
+	0x0fc4b600,
+	0x9800bcbb,
+	0x0d98050c,
+	0x040f9806,
+	0x0800e7f1,
+	0x015c21f5,
 	0xf001acf0,
-	0xb7f002a5,
-	0x50b3f000,
-	0xb6000c98,
-	0xbcbb0fc4,
-	0x010c9800,
-	0xf0020d98,
-	0x21f500e7,
-	0xacf0015c,
-	0x04a5f001,
-	0x4000b7f1,
-	0x9850b3f0,
-	0xc4b6000c,
-	0x00bcbb0f,
-	0x98050c98,
-	0x0f98060d,
-	0x00e7f104,
-	0x5c21f508,
-	0x0721f501,
-	0x0601f402,
-/* 0x054b: ctx_xfer_post */
-	0xf11412f4,
-	0xf04afc17,
-	0x27f00213,
-	0x0012d00d,
-	0x020721f5,
-/* 0x055c: ctx_xfer_done */
-	0x048f21f5,
-	0x000000f8,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
+	0xb7f104a5,
+	0xb3f03000,
+	0x000c9850,
+	0xbb0fc4b6,
+	0x0c9800bc,
+	0x0a0d9809,
+	0xf1080f98,
+	0xf50200e7,
+	0xf5015c21,
+	0xf4020721,
+	0x12f40601,
+/* 0x0585: ctx_xfer_post */
+	0xfc17f114,
+	0x0213f04a,
+	0xd00d27f0,
+	0x21f50012,
+/* 0x0596: ctx_xfer_done */
+	0x21f50207,
+	0x00f804a5,
 	0x00000000,
 	0x00000000,
 	0x00000000,