clk: hisi: add clk-hix5hd2.c
Signed-off-by: Haifeng Yan <haifeng.yan@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>wifi-calibration
Zhangfei Gao
Haojian Zhuang
parent
8b9dcb6cb7
commit
5efaf09021
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@ -0,0 +1,31 @@
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* Hisilicon Hix5hd2 Clock Controller
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The hix5hd2 clock controller generates and supplies clock to various
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controllers within the hix5hd2 SoC.
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Required Properties:
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- compatible: should be "hisilicon,hix5hd2-clock"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
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Examples:
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clock: clock@f8a22000 {
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compatible = "hisilicon,hix5hd2-clock";
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reg = <0xf8a22000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: uart@f8b00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8b00000 0x1000>;
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interrupts = <0 49 4>;
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clocks = <&clock HIX5HD2_FIXED_83M>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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@ -33,6 +33,7 @@ obj-$(CONFIG_COMMON_CLK_AT91) += at91/
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obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
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obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
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obj-$(CONFIG_ARCH_HIP04) += hisilicon/
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obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
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obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
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ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_ARCH_MMP) += mmp/
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@ -6,3 +6,4 @@ obj-y += clk.o clkgate-separated.o
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obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
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obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
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obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
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/*
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* Copyright (c) 2014 Linaro Ltd.
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* Copyright (c) 2014 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/of_address.h>
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#include <dt-bindings/clock/hix5hd2-clock.h>
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#include "clk.h"
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static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
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{ HIX5HD2_FIXED_1200M, "1200m", NULL, CLK_IS_ROOT, 1200000000, },
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{ HIX5HD2_FIXED_400M, "400m", NULL, CLK_IS_ROOT, 400000000, },
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{ HIX5HD2_FIXED_48M, "48m", NULL, CLK_IS_ROOT, 48000000, },
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{ HIX5HD2_FIXED_24M, "24m", NULL, CLK_IS_ROOT, 24000000, },
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{ HIX5HD2_FIXED_600M, "600m", NULL, CLK_IS_ROOT, 600000000, },
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{ HIX5HD2_FIXED_300M, "300m", NULL, CLK_IS_ROOT, 300000000, },
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{ HIX5HD2_FIXED_75M, "75m", NULL, CLK_IS_ROOT, 75000000, },
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{ HIX5HD2_FIXED_200M, "200m", NULL, CLK_IS_ROOT, 200000000, },
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{ HIX5HD2_FIXED_100M, "100m", NULL, CLK_IS_ROOT, 100000000, },
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{ HIX5HD2_FIXED_40M, "40m", NULL, CLK_IS_ROOT, 40000000, },
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{ HIX5HD2_FIXED_150M, "150m", NULL, CLK_IS_ROOT, 150000000, },
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{ HIX5HD2_FIXED_1728M, "1728m", NULL, CLK_IS_ROOT, 1728000000, },
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{ HIX5HD2_FIXED_28P8M, "28p8m", NULL, CLK_IS_ROOT, 28000000, },
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{ HIX5HD2_FIXED_432M, "432m", NULL, CLK_IS_ROOT, 432000000, },
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{ HIX5HD2_FIXED_345P6M, "345p6m", NULL, CLK_IS_ROOT, 345000000, },
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{ HIX5HD2_FIXED_288M, "288m", NULL, CLK_IS_ROOT, 288000000, },
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{ HIX5HD2_FIXED_60M, "60m", NULL, CLK_IS_ROOT, 60000000, },
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{ HIX5HD2_FIXED_750M, "750m", NULL, CLK_IS_ROOT, 750000000, },
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{ HIX5HD2_FIXED_500M, "500m", NULL, CLK_IS_ROOT, 500000000, },
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{ HIX5HD2_FIXED_54M, "54m", NULL, CLK_IS_ROOT, 54000000, },
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{ HIX5HD2_FIXED_27M, "27m", NULL, CLK_IS_ROOT, 27000000, },
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{ HIX5HD2_FIXED_1500M, "1500m", NULL, CLK_IS_ROOT, 1500000000, },
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{ HIX5HD2_FIXED_375M, "375m", NULL, CLK_IS_ROOT, 375000000, },
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{ HIX5HD2_FIXED_187M, "187m", NULL, CLK_IS_ROOT, 187000000, },
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{ HIX5HD2_FIXED_250M, "250m", NULL, CLK_IS_ROOT, 250000000, },
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{ HIX5HD2_FIXED_125M, "125m", NULL, CLK_IS_ROOT, 125000000, },
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{ HIX5HD2_FIXED_2P02M, "2m", NULL, CLK_IS_ROOT, 2000000, },
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{ HIX5HD2_FIXED_50M, "50m", NULL, CLK_IS_ROOT, 50000000, },
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{ HIX5HD2_FIXED_25M, "25m", NULL, CLK_IS_ROOT, 25000000, },
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{ HIX5HD2_FIXED_83M, "83m", NULL, CLK_IS_ROOT, 83333333, },
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};
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static const char *sfc_mux_p[] __initconst = {
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"24m", "150m", "200m", "100m", "75m", };
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static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
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static const char *sdio1_mux_p[] __initconst = {
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"75m", "100m", "50m", "15m", };
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static u32 sdio1_mux_table[] = {0, 1, 2, 3};
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static const char *fephy_mux_p[] __initconst = { "25m", "125m"};
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static u32 fephy_mux_table[] = {0, 1};
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static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
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{ HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
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CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
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{ HIX5HD2_MMC_MUX, "mmc_mux", sdio1_mux_p, ARRAY_SIZE(sdio1_mux_p),
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CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio1_mux_table, },
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{ HIX5HD2_FEPHY_MUX, "fephy_mux",
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fephy_mux_p, ARRAY_SIZE(fephy_mux_p),
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CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
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};
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static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
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/*sfc*/
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{ HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux",
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CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
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{ HIX5HD2_SFC_RST, "rst_sfc", "clk_sfc",
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CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
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/*sdio1*/
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{ HIX5HD2_MMC_BIU_CLK, "clk_mmc_biu", "200m",
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CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
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{ HIX5HD2_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
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CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
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{ HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu",
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CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
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};
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static void __init hix5hd2_clk_init(struct device_node *np)
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{
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struct hisi_clock_data *clk_data;
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clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS);
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if (!clk_data)
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return;
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hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks,
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ARRAY_SIZE(hix5hd2_fixed_rate_clks),
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clk_data);
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hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks),
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clk_data);
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hisi_clk_register_gate(hix5hd2_gate_clks,
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ARRAY_SIZE(hix5hd2_gate_clks), clk_data);
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}
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CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);
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@ -0,0 +1,58 @@
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/*
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* Copyright (c) 2014 Linaro Ltd.
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* Copyright (c) 2014 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#ifndef __DTS_HIX5HD2_CLOCK_H
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#define __DTS_HIX5HD2_CLOCK_H
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/* fixed rate */
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#define HIX5HD2_FIXED_1200M 1
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#define HIX5HD2_FIXED_400M 2
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#define HIX5HD2_FIXED_48M 3
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#define HIX5HD2_FIXED_24M 4
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#define HIX5HD2_FIXED_600M 5
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#define HIX5HD2_FIXED_300M 6
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#define HIX5HD2_FIXED_75M 7
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#define HIX5HD2_FIXED_200M 8
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#define HIX5HD2_FIXED_100M 9
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#define HIX5HD2_FIXED_40M 10
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#define HIX5HD2_FIXED_150M 11
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#define HIX5HD2_FIXED_1728M 12
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#define HIX5HD2_FIXED_28P8M 13
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#define HIX5HD2_FIXED_432M 14
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#define HIX5HD2_FIXED_345P6M 15
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#define HIX5HD2_FIXED_288M 16
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#define HIX5HD2_FIXED_60M 17
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#define HIX5HD2_FIXED_750M 18
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#define HIX5HD2_FIXED_500M 19
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#define HIX5HD2_FIXED_54M 20
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#define HIX5HD2_FIXED_27M 21
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#define HIX5HD2_FIXED_1500M 22
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#define HIX5HD2_FIXED_375M 23
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#define HIX5HD2_FIXED_187M 24
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#define HIX5HD2_FIXED_250M 25
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#define HIX5HD2_FIXED_125M 26
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#define HIX5HD2_FIXED_2P02M 27
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#define HIX5HD2_FIXED_50M 28
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#define HIX5HD2_FIXED_25M 29
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#define HIX5HD2_FIXED_83M 30
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/* mux clocks */
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#define HIX5HD2_SFC_MUX 64
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#define HIX5HD2_MMC_MUX 65
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#define HIX5HD2_FEPHY_MUX 66
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/* gate clocks */
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#define HIX5HD2_SFC_RST 128
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#define HIX5HD2_SFC_CLK 129
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#define HIX5HD2_MMC_CIU_CLK 130
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#define HIX5HD2_MMC_BIU_CLK 131
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#define HIX5HD2_MMC_CIU_RST 132
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#define HIX5HD2_NR_CLKS 256
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#endif /* __DTS_HIX5HD2_CLOCK_H */
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