A first set of pin control fixes for the v3.15 series:
- Fix a couple of barnsjukdomar on the Rockchip driver. - Remove an idiotic debug print I happened to leave behind in the Nomadik driver. - Fixup the Qualcomm MSM interrupt handling code for the TLMM v2. - Three patches renaming the Broadcom Capri driver to BCM28155. This has been falling between the chairs for some time due to some cross-tree synchronization misunderstandings, now I'm fed up with this and just rename it in this -rc1 phase. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTTPPzAAoJEEEQszewGV1zSBgP/iMS9y9LAouPmzkXseCeT4aM eb2pEi1wtOSWCeGNMIx4X1GRkbHS+T+5Wk6dmh46RUn/8b1HY4gkLoJLnrQGML1l zS9tdDyURGmGYuVAr0ghLq0LTruvcViCQageRzO8yllTkJb8Tf6rfKE2+y9BsGRH CdBIE9/XYP2Z2Wwd0fLAPMFpa9wPz8eNeF7XGyQ20+DSuRzNMmDq6AUhmlCfIMnL TxlJIT1vpAAt/e3wcRvmr2n/Nrlz28ajP/VmzSm2dSqTajy8ofWqgFwQLiItJJ3q VuJto3eKy+xGT4IVO+ozXCZd0kDgaAeiz7PNWHpbFBec0y4QFmVFxtPpw/Zff7RH 136Vh0KahX47TaJ1GGvB5622OLjsQzwH2TY24Sn9WRzNT8VS0pv2F3RQk8tVrWrd fquQksuMEaCay+MHcBhI1mJlQcgTFJNsenmY8KOIjFykeBz5x6bOtBkbOCjzuogr yVgaOW/zV7b0zFQ6Vv9eZFf7WYhBXE7w1Im5D2EMR9mJpNBWbj9A8GQpCjc0+VXB jN2hWmj5qQtQW6z67VEn3l8Mqzpazsu61zbcB3F4Ma0m247vakIkk5I8GMmLW3/c UMr6RG2IHIaECNdS1Ir1UkBnDCFb7CQq3j0Bh2UynyU9jKGtRZU/P7SdD7LqHsi+ Q56kdNSbYdRPpjPWmZUA =i5qY -----END PGP SIGNATURE----- Merge tag 'pinctrl-v3.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pincontrol fixes from Linus Walleij: "A first set of pin control fixes for the v3.15 series: - Fix a couple of barnsjukdomar on the Rockchip driver. - Remove an idiotic debug print I happened to leave behind in the Nomadik driver. - Fixup the Qualcomm MSM interrupt handling code for the TLMM v2. - Three patches renaming the Broadcom Capri driver to BCM28155. This has been falling between the chairs for some time due to some cross-tree synchronization misunderstandings, now I'm fed up with this and just rename it in this -rc1 phase" * tag 'pinctrl-v3.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: fix typo in bindings documentation Update bcm_defconfig with new pinctrl CONFIG pinctrl: Rename Broadcom Capri pinctrl driver pinctrl: msm: Correct interrupt code for TLMM v2 pinctrl: nomadik: delete stray debug print pinctrl: rockchip: handle first half of rk3188-bank0 correctly pinctrl: rockchip: add return value to rockchip_set_mux pinctrl: rockchip: fix offset of mux registers for rk3188
This commit is contained in:
commit
5f63517cbf
|
@ -119,7 +119,7 @@ Optional Properties (for HDMI pins):
|
|||
Example:
|
||||
// pin controller node
|
||||
pinctrl@35004800 {
|
||||
compatible = "brcmbcm11351-pinctrl";
|
||||
compatible = "brcm,bcm11351-pinctrl";
|
||||
reg = <0x35004800 0x430>;
|
||||
|
||||
// pin configuration node
|
||||
|
|
|
@ -132,7 +132,7 @@ CONFIG_CRC_ITU_T=y
|
|||
CONFIG_CRC7=y
|
||||
CONFIG_XZ_DEC=y
|
||||
CONFIG_AVERAGE=y
|
||||
CONFIG_PINCTRL_CAPRI=y
|
||||
CONFIG_PINCTRL_BCM281XX=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_BCM_KONA_WDT=y
|
||||
CONFIG_BCM_KONA_WDT_DEBUG=y
|
||||
|
|
|
@ -104,16 +104,16 @@ config PINCTRL_BCM2835
|
|||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_CAPRI
|
||||
bool "Broadcom Capri pinctrl driver"
|
||||
config PINCTRL_BCM281XX
|
||||
bool "Broadcom BCM281xx pinctrl driver"
|
||||
depends on OF
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
select REGMAP_MMIO
|
||||
help
|
||||
Say Y here to support Broadcom Capri pinctrl driver, which is used for
|
||||
the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351,
|
||||
Say Y here to support Broadcom BCM281xx pinctrl driver, which is used
|
||||
for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351,
|
||||
BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
|
||||
framework. GPIO is provided by a separate GPIO driver.
|
||||
|
||||
|
|
|
@ -21,7 +21,7 @@ obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
|
|||
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
|
||||
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
|
||||
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
|
||||
obj-$(CONFIG_PINCTRL_CAPRI) += pinctrl-capri.o
|
||||
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
|
||||
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
|
||||
|
|
1461
drivers/pinctrl/pinctrl-bcm281xx.c
Normal file
1461
drivers/pinctrl/pinctrl-bcm281xx.c
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
@ -665,7 +665,10 @@ static void msm_gpio_irq_ack(struct irq_data *d)
|
|||
spin_lock_irqsave(&pctrl->lock, flags);
|
||||
|
||||
val = readl(pctrl->regs + g->intr_status_reg);
|
||||
val &= ~BIT(g->intr_status_bit);
|
||||
if (g->intr_ack_high)
|
||||
val |= BIT(g->intr_status_bit);
|
||||
else
|
||||
val &= ~BIT(g->intr_status_bit);
|
||||
writel(val, pctrl->regs + g->intr_status_reg);
|
||||
|
||||
if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
|
||||
|
@ -744,6 +747,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
break;
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
val |= BIT(g->intr_detection_bit);
|
||||
val |= BIT(g->intr_polarity_bit);
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
break;
|
||||
|
|
|
@ -84,6 +84,7 @@ struct msm_pingroup {
|
|||
|
||||
unsigned intr_enable_bit:5;
|
||||
unsigned intr_status_bit:5;
|
||||
unsigned intr_ack_high:1;
|
||||
|
||||
unsigned intr_target_bit:5;
|
||||
unsigned intr_raw_status_bit:5;
|
||||
|
|
|
@ -877,7 +877,6 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|||
struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
|
||||
u32 status;
|
||||
|
||||
pr_err("PLONK IRQ %d\n", irq);
|
||||
clk_enable(nmk_chip->clk);
|
||||
status = readl(nmk_chip->addr + NMK_GPIO_IS);
|
||||
clk_disable(nmk_chip->clk);
|
||||
|
|
|
@ -342,7 +342,7 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
|
|||
* @pin: pin to change
|
||||
* @mux: new mux function to set
|
||||
*/
|
||||
static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
||||
static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
||||
{
|
||||
struct rockchip_pinctrl *info = bank->drvdata;
|
||||
void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
|
||||
|
@ -350,6 +350,20 @@ static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
|||
u8 bit;
|
||||
u32 data;
|
||||
|
||||
/*
|
||||
* The first 16 pins of rk3188_bank0 are always gpios and do not have
|
||||
* a mux register at all.
|
||||
*/
|
||||
if (bank->bank_type == RK3188_BANK0 && pin < 16) {
|
||||
if (mux != RK_FUNC_GPIO) {
|
||||
dev_err(info->dev,
|
||||
"pin %d only supports a gpio mux\n", pin);
|
||||
return -ENOTSUPP;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
|
||||
bank->bank_num, pin, mux);
|
||||
|
||||
|
@ -365,6 +379,8 @@ static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
|
|||
writel(data, reg);
|
||||
|
||||
spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define RK2928_PULL_OFFSET 0x118
|
||||
|
@ -560,7 +576,7 @@ static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
const unsigned int *pins = info->groups[group].pins;
|
||||
const struct rockchip_pin_config *data = info->groups[group].data;
|
||||
struct rockchip_pin_bank *bank;
|
||||
int cnt;
|
||||
int cnt, ret = 0;
|
||||
|
||||
dev_dbg(info->dev, "enable function %s group %s\n",
|
||||
info->functions[selector].name, info->groups[group].name);
|
||||
|
@ -571,8 +587,18 @@ static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
|
|||
*/
|
||||
for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
|
||||
bank = pin_to_bank(info, pins[cnt]);
|
||||
rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
|
||||
data[cnt].func);
|
||||
ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
|
||||
data[cnt].func);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
/* revert the already done pin settings */
|
||||
for (cnt--; cnt >= 0; cnt--)
|
||||
rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
@ -607,7 +633,7 @@ static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|||
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct rockchip_pin_bank *bank;
|
||||
struct gpio_chip *chip;
|
||||
int pin;
|
||||
int pin, ret;
|
||||
u32 data;
|
||||
|
||||
chip = range->gc;
|
||||
|
@ -617,7 +643,9 @@ static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|||
dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
|
||||
offset, range->name, pin, input ? "input" : "output");
|
||||
|
||||
rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
|
||||
ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
|
||||
/* set bit to 1 for output, 0 for input */
|
||||
|
@ -1144,9 +1172,13 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
u32 polarity;
|
||||
u32 level;
|
||||
u32 data;
|
||||
int ret;
|
||||
|
||||
/* make sure the pin is configured as gpio input */
|
||||
rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
|
||||
ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
|
||||
data &= ~mask;
|
||||
writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
|
||||
|
@ -1534,7 +1566,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
|
|||
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
|
||||
.label = "RK3188-GPIO",
|
||||
.type = RK3188,
|
||||
.mux_offset = 0x68,
|
||||
.mux_offset = 0x60,
|
||||
.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in a new issue