Addition of the CPU clock configuration data for Exynos4412
Prime SoC variant. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJYZS0+AAoJEE1bIKeAnHqL/dgP+gM1HRhx/EEgCtWlUezdTQiV kdVEuvMi6/uVC4h4ElG52q3yhsT3A949Fge+I4HKvFfNhwYhA6OGfF2CY/uSSt7W GgV9yZxnfAuRM6IBIhCfh4DPczhCDAZiViYzWT2qkMA2H8in134b3nug/aF3cINI OeJNkrVseVZe5jmaTG+NsPPwh9/2t2lTA5tJ40P7JTb7oneC2Q4JEfz/vqx75RNv 6/w5Ve4Kz1L3oXcAWx3OxUUfK9Obi2xeH6lXttSKdcezTT0aMYLnehnkl/3A3qTC P24c5CzoFA62VL1pq+Aq2/r2loHKo1Sm6PnBCw/cWz9dAtU2lch6RySbk5cY2vgu 5N0J7vtuP9XevuepmWeNJfB130FvJVPuLGUiDED7TEFE0DtmY/hHAJm8f/qNpvp6 qbE2Tb9HTUQlykSX7c2cD5HruOB0lKBpEgPhBfregVX/oJ+dtxFwNcna051prXUy z+YWEWeHkDGaZeaRej0r4S7o6ebp+S+fOivqpRY5p+9fGCF47ZgwbUE8PwPssyXE 12mp5getjtnVUgrrWhSmpxKNC/RYs/6W2k4iO4WMXc2TxHF21NfFtQwCzjTDDuFR /x6OdoDQ9Cp8eaBiwNqzYqlcKv6wr5oK0sdljb5XWjAa96KmIECmxCMnc4aB+c3n tPwryTHL5gNYalTQGaCB =bMk6 -----END PGP SIGNATURE----- Merge tag 'clk-v4.11-exynos4-pll' of git://linuxtv.org/snawrocki/samsung into next/dt Addition of the CPU clock configuration data for Exynos4412 Prime SoC variant.
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@ -1298,6 +1298,8 @@ static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst =
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};
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static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
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PLL_35XX_RATE(1704000000, 213, 3, 0),
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PLL_35XX_RATE(1600000000, 200, 3, 0),
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PLL_35XX_RATE(1500000000, 250, 4, 0),
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PLL_35XX_RATE(1400000000, 175, 3, 0),
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PLL_35XX_RATE(1300000000, 325, 6, 0),
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@ -1421,6 +1423,8 @@ static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
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(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
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static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
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{ 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
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{ 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
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{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
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{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
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{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
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