[TG3]: Power down/up 5906 PHY correctly.
The 5906 PHY requires a special register bit to power down and up the PHY. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -959,6 +959,13 @@ static int tg3_phy_reset(struct tg3 *tp)
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u32 phy_status;
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int err;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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u32 val;
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val = tr32(GRC_MISC_CFG);
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tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
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udelay(40);
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}
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err = tg3_readphy(tp, MII_BMSR, &phy_status);
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err |= tg3_readphy(tp, MII_BMSR, &phy_status);
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if (err != 0)
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@ -1170,7 +1177,15 @@ static void tg3_power_down_phy(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
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return;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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u32 val;
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tg3_bmcr_reset(tp);
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val = tr32(GRC_MISC_CFG);
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tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
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udelay(40);
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return;
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} else {
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
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@ -1350,6 +1350,7 @@
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#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
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#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
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#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
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#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
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#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
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#define GRC_LOCAL_CTRL 0x00006808
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#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
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