ASoC: rt5677: fixed wrong DMIC ref clock
DMIC clock source is not from codec system clock directly. it is generated from the division of system clock. And it should be 256 * sample rate of AIF1. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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@ -904,7 +904,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
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{
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struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
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struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
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int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
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int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8);
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if (idx < 0)
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dev_err(codec->dev, "Failed to set DMIC clock\n");
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