clocksource: arch_timer: Push the read/write wrappers deeper
We're going to introduce support to read and write the memory mapped timer registers in the next patch, so push the cp15 read/write functions one level deeper. This simplifies the next patch and makes it clearer what's going on. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <Marc.Zyngier@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
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@ -18,7 +18,7 @@ int arch_timer_arch_init(void);
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* the code. At least it does so with a recent GCC (4.6.3).
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* the code. At least it does so with a recent GCC (4.6.3).
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*/
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*/
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static __always_inline
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static __always_inline
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void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val)
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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switch (reg) {
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@ -44,7 +44,7 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val)
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}
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}
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static __always_inline
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static __always_inline
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u32 arch_timer_reg_read(int access, enum arch_timer_reg reg)
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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{
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u32 val = 0;
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u32 val = 0;
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@ -32,7 +32,7 @@
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* the code.
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* the code.
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*/
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*/
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static __always_inline
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static __always_inline
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void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val)
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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switch (reg) {
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@ -58,7 +58,7 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val)
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}
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}
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static __always_inline
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static __always_inline
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u32 arch_timer_reg_read(int access, enum arch_timer_reg reg)
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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{
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u32 val;
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u32 val;
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@ -43,14 +43,28 @@ static bool arch_timer_use_virtual = true;
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* Architected system timer support.
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* Architected system timer support.
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*/
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*/
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static __always_inline
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void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
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struct clock_event_device *clk)
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{
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arch_timer_reg_write_cp15(access, reg, val);
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}
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static __always_inline
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u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
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struct clock_event_device *clk)
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{
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return arch_timer_reg_read_cp15(access, reg);
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}
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static __always_inline irqreturn_t timer_handler(const int access,
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static __always_inline irqreturn_t timer_handler(const int access,
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struct clock_event_device *evt)
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struct clock_event_device *evt)
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{
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{
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unsigned long ctrl;
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
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if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
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if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
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ctrl |= ARCH_TIMER_CTRL_IT_MASK;
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ctrl |= ARCH_TIMER_CTRL_IT_MASK;
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
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evt->event_handler(evt);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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@ -72,15 +86,16 @@ static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
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return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
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return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
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}
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}
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static __always_inline void timer_set_mode(const int access, int mode)
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static __always_inline void timer_set_mode(const int access, int mode,
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struct clock_event_device *clk)
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{
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{
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unsigned long ctrl;
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unsigned long ctrl;
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switch (mode) {
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switch (mode) {
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_SHUTDOWN:
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
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ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
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ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
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break;
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break;
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default:
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default:
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break;
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break;
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@ -90,36 +105,37 @@ static __always_inline void timer_set_mode(const int access, int mode)
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static void arch_timer_set_mode_virt(enum clock_event_mode mode,
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static void arch_timer_set_mode_virt(enum clock_event_mode mode,
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struct clock_event_device *clk)
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struct clock_event_device *clk)
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{
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{
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timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
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timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
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}
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}
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static void arch_timer_set_mode_phys(enum clock_event_mode mode,
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static void arch_timer_set_mode_phys(enum clock_event_mode mode,
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struct clock_event_device *clk)
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struct clock_event_device *clk)
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{
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{
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timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
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timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
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}
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}
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static __always_inline void set_next_event(const int access, unsigned long evt)
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static __always_inline void set_next_event(const int access, unsigned long evt,
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struct clock_event_device *clk)
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{
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{
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unsigned long ctrl;
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unsigned long ctrl;
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
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ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
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ctrl |= ARCH_TIMER_CTRL_ENABLE;
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ctrl |= ARCH_TIMER_CTRL_ENABLE;
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ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
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ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
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arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
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arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
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arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
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}
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}
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static int arch_timer_set_next_event_virt(unsigned long evt,
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static int arch_timer_set_next_event_virt(unsigned long evt,
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struct clock_event_device *unused)
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struct clock_event_device *clk)
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{
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{
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set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
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set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
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return 0;
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return 0;
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}
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}
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static int arch_timer_set_next_event_phys(unsigned long evt,
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static int arch_timer_set_next_event_phys(unsigned long evt,
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struct clock_event_device *unused)
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struct clock_event_device *clk)
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{
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{
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set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
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set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
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return 0;
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return 0;
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}
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}
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