ASoC: tlv320aic32x4: Use snd_soc_update_bits() in aic32x4_set_dai_fmt()
Make the code easier to read by using snd_soc_update_bits() over read/modify/write sequences. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -614,16 +614,9 @@ static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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u8 iface_reg_1;
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u8 iface_reg_2;
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u8 iface_reg_3;
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iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
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iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
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iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
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iface_reg_2 = 0;
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iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
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iface_reg_3 = iface_reg_3 & ~(1 << 3);
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u8 iface_reg_1 = 0;
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u8 iface_reg_2 = 0;
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u8 iface_reg_3 = 0;
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/* set master/slave audio interface */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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@ -643,13 +636,13 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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case SND_SOC_DAIFMT_DSP_A:
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iface_reg_1 |= (AIC32X4_DSP_MODE <<
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AIC32X4_IFACE1_DATATYPE_SHIFT);
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iface_reg_3 |= (1 << 3); /* invert bit clock */
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iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
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iface_reg_2 = 0x01; /* add offset 1 */
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break;
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case SND_SOC_DAIFMT_DSP_B:
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iface_reg_1 |= (AIC32X4_DSP_MODE <<
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AIC32X4_IFACE1_DATATYPE_SHIFT);
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iface_reg_3 |= (1 << 3); /* invert bit clock */
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iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
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@ -664,9 +657,14 @@ static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
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return -EINVAL;
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}
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snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
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snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
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snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
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snd_soc_update_bits(codec, AIC32X4_IFACE1,
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AIC32X4_IFACE1_DATATYPE_MASK |
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AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
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snd_soc_update_bits(codec, AIC32X4_IFACE2,
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AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
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snd_soc_update_bits(codec, AIC32X4_IFACE3,
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AIC32X4_BCLKINV_MASK, iface_reg_3);
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return 0;
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}
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