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stmmac: fix csr clock divisor for 300MHz 

This patch is to fix the csr clock in case of 300MHz is provided.

Reported-by: Kent Borg <Kent.Borg@csr.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
steinar/wifi_calib_4_9_kernel
Giuseppe CAVALLARO 2015-11-26 08:35:42 +01:00 committed by David S. Miller
parent ac316c783d
commit 61adcc03bd
1 changed files with 1 additions and 1 deletions
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2
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
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@ -185,7 +185,7 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
priv->clk_csr = STMMAC_CSR_100_150M;
else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
priv->clk_csr = STMMAC_CSR_150_250M;
else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
priv->clk_csr = STMMAC_CSR_250_300M;
}
}