intel-iommu: move DMA PTE defs out of dma_remapping.h
DMA_PTE_READ/WRITE are needed by kvm. Signed-off-by: Mark McLoughlin <markmc@redhat.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -128,6 +128,28 @@ struct context_entry {
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do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
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#define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
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/*
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* 0: readable
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* 1: writable
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* 2-6: reserved
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* 7: super page
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* 8-11: available
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* 12-63: Host physcial address
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*/
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struct dma_pte {
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u64 val;
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};
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#define dma_clear_pte(p) do {(p).val = 0;} while (0)
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#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
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#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
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#define dma_set_pte_prot(p, prot) \
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do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
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#define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK)
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#define dma_set_pte_addr(p, addr) do {\
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(p).val |= ((addr) & VTD_PAGE_MASK); } while (0)
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#define dma_pte_present(p) (((p).val & 3) != 0)
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static void flush_unmaps_timeout(unsigned long data);
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DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
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@ -11,31 +11,9 @@
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struct root_entry;
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/*
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* 0: readable
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* 1: writable
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* 2-6: reserved
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* 7: super page
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* 8-11: available
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* 12-63: Host physcial address
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*/
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struct dma_pte {
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u64 val;
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};
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#define dma_clear_pte(p) do {(p).val = 0;} while (0)
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#define DMA_PTE_READ (1)
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#define DMA_PTE_WRITE (2)
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#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
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#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
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#define dma_set_pte_prot(p, prot) \
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do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
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#define dma_pte_addr(p) ((p).val & VTD_PAGE_MASK)
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#define dma_set_pte_addr(p, addr) do {\
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(p).val |= ((addr) & VTD_PAGE_MASK); } while (0)
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#define dma_pte_present(p) (((p).val & 3) != 0)
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struct intel_iommu;
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struct dmar_domain {
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