Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, pci: Correct spelling in a comment x86: Simplify bound checks in the MTRR code x86: EDAC: carve out AMD MCE decoding logic initcalls: Add early_initcall() for modules x86: EDAC: MCE: Fix MCE decoding callback logic
This commit is contained in:
commit
624235c5b3
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@ -133,6 +133,8 @@ static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void enable_p5_mce(void) {}
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static inline void enable_p5_mce(void) {}
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#endif
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#endif
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extern void (*x86_mce_decode_callback)(struct mce *m);
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void mce_setup(struct mce *m);
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void mce_setup(struct mce *m);
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void mce_log(struct mce *m);
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct sys_device, mce_dev);
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DECLARE_PER_CPU(struct sys_device, mce_dev);
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@ -85,6 +85,18 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
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static DEFINE_PER_CPU(struct mce, mces_seen);
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static DEFINE_PER_CPU(struct mce, mces_seen);
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static int cpu_missing;
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static int cpu_missing;
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static void default_decode_mce(struct mce *m)
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{
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pr_emerg("No human readable MCE decoding support on this CPU type.\n");
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pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
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}
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/*
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* CPU/chipset specific EDAC code can register a callback here to print
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* MCE errors in a human-readable form:
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*/
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void (*x86_mce_decode_callback)(struct mce *m) = default_decode_mce;
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EXPORT_SYMBOL(x86_mce_decode_callback);
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/* MCA banks polled by the period polling timer for corrected events */
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/* MCA banks polled by the period polling timer for corrected events */
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DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
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DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
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@ -165,46 +177,46 @@ void mce_log(struct mce *mce)
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set_bit(0, &mce_need_notify);
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set_bit(0, &mce_need_notify);
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}
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}
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void __weak decode_mce(struct mce *m)
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{
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return;
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}
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static void print_mce(struct mce *m)
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static void print_mce(struct mce *m)
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{
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{
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printk(KERN_EMERG
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pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
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"CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
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m->extcpu, m->mcgstatus, m->bank, m->status);
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m->extcpu, m->mcgstatus, m->bank, m->status);
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if (m->ip) {
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if (m->ip) {
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printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
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pr_emerg("RIP%s %02x:<%016Lx> ",
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!(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
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!(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
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m->cs, m->ip);
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m->cs, m->ip);
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if (m->cs == __KERNEL_CS)
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if (m->cs == __KERNEL_CS)
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print_symbol("{%s}", m->ip);
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print_symbol("{%s}", m->ip);
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printk(KERN_CONT "\n");
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pr_cont("\n");
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}
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}
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printk(KERN_EMERG "TSC %llx ", m->tsc);
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if (m->addr)
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printk(KERN_CONT "ADDR %llx ", m->addr);
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if (m->misc)
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printk(KERN_CONT "MISC %llx ", m->misc);
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printk(KERN_CONT "\n");
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printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
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m->cpuvendor, m->cpuid, m->time, m->socketid,
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m->apicid);
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decode_mce(m);
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pr_emerg("TSC %llx ", m->tsc);
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if (m->addr)
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pr_cont("ADDR %llx ", m->addr);
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if (m->misc)
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pr_cont("MISC %llx ", m->misc);
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pr_cont("\n");
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pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
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m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
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/*
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* Print out human-readable details about the MCE error,
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* (if the CPU has an implementation for that):
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*/
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x86_mce_decode_callback(m);
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}
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}
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static void print_mce_head(void)
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static void print_mce_head(void)
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{
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{
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printk(KERN_EMERG "\nHARDWARE ERROR\n");
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pr_emerg("\nHARDWARE ERROR\n");
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}
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}
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static void print_mce_tail(void)
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static void print_mce_tail(void)
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{
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{
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printk(KERN_EMERG "This is not a software problem!\n"
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pr_emerg("This is not a software problem!\n");
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"Run through mcelog --ascii to decode and contact your hardware vendor\n");
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}
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}
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#define PANIC_TIMEOUT 5 /* 5 seconds */
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#define PANIC_TIMEOUT 5 /* 5 seconds */
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@ -218,6 +230,7 @@ static atomic_t mce_fake_paniced;
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static void wait_for_panic(void)
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static void wait_for_panic(void)
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{
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{
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long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
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long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
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preempt_disable();
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preempt_disable();
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local_irq_enable();
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local_irq_enable();
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while (timeout-- > 0)
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while (timeout-- > 0)
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@ -285,6 +298,7 @@ static void mce_panic(char *msg, struct mce *final, char *exp)
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static int msr_to_offset(u32 msr)
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static int msr_to_offset(u32 msr)
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{
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{
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unsigned bank = __get_cpu_var(injectm.bank);
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unsigned bank = __get_cpu_var(injectm.bank);
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if (msr == rip_msr)
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if (msr == rip_msr)
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return offsetof(struct mce, ip);
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return offsetof(struct mce, ip);
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if (msr == MSR_IA32_MCx_STATUS(bank))
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if (msr == MSR_IA32_MCx_STATUS(bank))
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@ -96,17 +96,24 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
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unsigned long long base, size;
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unsigned long long base, size;
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char *ptr;
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char *ptr;
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char line[LINE_SIZE];
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char line[LINE_SIZE];
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int length;
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size_t linelen;
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size_t linelen;
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if (!capable(CAP_SYS_ADMIN))
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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return -EPERM;
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if (!len)
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return -EINVAL;
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memset(line, 0, LINE_SIZE);
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memset(line, 0, LINE_SIZE);
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if (len > LINE_SIZE)
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len = LINE_SIZE;
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length = len;
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if (copy_from_user(line, buf, len - 1))
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length--;
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if (length > LINE_SIZE - 1)
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length = LINE_SIZE - 1;
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if (length < 0)
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return -EINVAL;
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if (copy_from_user(line, buf, length))
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return -EFAULT;
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return -EFAULT;
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linelen = strlen(line);
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linelen = strlen(line);
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@ -35,7 +35,7 @@ int iommu_detected __read_mostly = 0;
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/*
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/*
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* This variable becomes 1 if iommu=pt is passed on the kernel command line.
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* This variable becomes 1 if iommu=pt is passed on the kernel command line.
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* If this variable is 1, IOMMU implementations do no DMA ranslation for
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* If this variable is 1, IOMMU implementations do no DMA translation for
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* devices and allow every device to access to whole physical memory. This is
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* devices and allow every device to access to whole physical memory. This is
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* useful if a user want to use an IOMMU only for KVM device assignment to
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* useful if a user want to use an IOMMU only for KVM device assignment to
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* guests and not for driver dma translation.
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* guests and not for driver dma translation.
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@ -47,6 +47,18 @@ config EDAC_DEBUG_VERBOSE
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Source file name and line number where debugging message
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Source file name and line number where debugging message
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printed will be added to debugging message.
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printed will be added to debugging message.
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config EDAC_DECODE_MCE
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tristate "Decode MCEs in human-readable form (only on AMD for now)"
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depends on CPU_SUP_AMD && X86_MCE
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default y
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---help---
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Enable this option if you want to decode Machine Check Exceptions
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occuring on your machine in human-readable form.
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You should definitely say Y here in case you want to decode MCEs
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which occur really early upon boot, before the module infrastructure
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has been initialized.
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config EDAC_MM_EDAC
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config EDAC_MM_EDAC
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tristate "Main Memory EDAC (Error Detection And Correction) reporting"
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tristate "Main Memory EDAC (Error Detection And Correction) reporting"
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help
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help
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@ -59,7 +71,7 @@ config EDAC_MM_EDAC
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config EDAC_AMD64
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
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tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
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depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && CPU_SUP_AMD
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depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
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help
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help
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Support for error detection and correction on the AMD 64
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Support for error detection and correction on the AMD 64
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Families of Memory Controllers (K8, F10h and F11h)
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Families of Memory Controllers (K8, F10h and F11h)
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@ -6,7 +6,6 @@
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# GNU General Public License.
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# GNU General Public License.
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#
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#
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obj-$(CONFIG_EDAC) := edac_stub.o
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obj-$(CONFIG_EDAC) := edac_stub.o
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obj-$(CONFIG_EDAC_MM_EDAC) += edac_core.o
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obj-$(CONFIG_EDAC_MM_EDAC) += edac_core.o
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@ -17,9 +16,7 @@ ifdef CONFIG_PCI
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edac_core-objs += edac_pci.o edac_pci_sysfs.o
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edac_core-objs += edac_pci.o edac_pci_sysfs.o
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endif
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endif
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ifdef CONFIG_CPU_SUP_AMD
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obj-$(CONFIG_EDAC_DECODE_MCE) += edac_mce_amd.o
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edac_core-objs += edac_mce_amd.o
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endif
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obj-$(CONFIG_EDAC_AMD76X) += amd76x_edac.o
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obj-$(CONFIG_EDAC_AMD76X) += amd76x_edac.o
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obj-$(CONFIG_EDAC_CPC925) += cpc925_edac.o
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obj-$(CONFIG_EDAC_CPC925) += cpc925_edac.o
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@ -3,6 +3,7 @@
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static bool report_gart_errors;
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static bool report_gart_errors;
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static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
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static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
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static void (*orig_mce_callback)(struct mce *m);
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void amd_report_gart_errors(bool v)
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void amd_report_gart_errors(bool v)
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{
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{
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@ -362,7 +363,7 @@ static inline void amd_decode_err_code(unsigned int ec)
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pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
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pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
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}
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}
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void decode_mce(struct mce *m)
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static void amd_decode_mce(struct mce *m)
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{
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{
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struct err_regs regs;
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struct err_regs regs;
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int node, ecc;
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int node, ecc;
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@ -420,3 +421,32 @@ void decode_mce(struct mce *m)
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amd_decode_err_code(m->status & 0xffff);
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amd_decode_err_code(m->status & 0xffff);
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}
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}
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static int __init mce_amd_init(void)
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{
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/*
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* We can decode MCEs for Opteron and later CPUs:
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*/
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
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(boot_cpu_data.x86 >= 0xf)) {
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/* safe the default decode mce callback */
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orig_mce_callback = x86_mce_decode_callback;
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x86_mce_decode_callback = amd_decode_mce;
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}
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return 0;
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}
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early_initcall(mce_amd_init);
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#ifdef MODULE
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static void __exit mce_amd_exit(void)
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{
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x86_mce_decode_callback = orig_mce_callback;
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}
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MODULE_DESCRIPTION("AMD MCE decoder");
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MODULE_ALIAS("edac-mce-amd");
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MODULE_LICENSE("GPL");
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module_exit(mce_amd_exit);
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#endif
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@ -271,6 +271,7 @@ void __init parse_early_options(char *cmdline);
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#else /* MODULE */
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#else /* MODULE */
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/* Don't use these in modules, but some people do... */
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/* Don't use these in modules, but some people do... */
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#define early_initcall(fn) module_init(fn)
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#define core_initcall(fn) module_init(fn)
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#define core_initcall(fn) module_init(fn)
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#define postcore_initcall(fn) module_init(fn)
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#define postcore_initcall(fn) module_init(fn)
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#define arch_initcall(fn) module_init(fn)
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#define arch_initcall(fn) module_init(fn)
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Reference in a new issue