PCI: layerscape: Add Freescale Layerscape PCIe driver
Add support for Freescale Layerscape PCIe controller. This driver re-uses the Synopsis DesignWare core code. [bhelgaas: add Kconfig dependency on CONFIG_ARM] Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
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Documentation/devicetree/bindings/pci/layerscape-pci.txt
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Documentation/devicetree/bindings/pci/layerscape-pci.txt
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@ -0,0 +1,42 @@
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Freescale Layerscape PCIe controller
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
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- reg: base addresses and lengths of the PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The interrupt that is asserted for controller interrupts
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- fsl,pcie-scfg: Must include two entries.
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The first entry must be a link to the SCFG device node
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The second entry must be '0' or '1' based on physical PCIe controller index.
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This is used to get SCFG PEXN registers
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Example:
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pcie@3400000 {
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compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
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0x40 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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fsl,pcie-scfg = <&scfg 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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};
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10
MAINTAINERS
10
MAINTAINERS
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@ -6983,6 +6983,16 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/xgene-pci.txt
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F: drivers/pci/host/pci-xgene.c
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PCI DRIVER FOR FREESCALE LAYERSCAPE
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M: Minghuan Lian <minghuan.Lian@freescale.com>
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M: Mingkai Hu <mingkai.hu@freescale.com>
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M: Roy Zang <tie-fei.zang@freescale.com>
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L: linuxppc-dev@lists.ozlabs.org
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org
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S: Maintained
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F: drivers/pci/host/*layerscape*
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PCI DRIVER FOR IMX6
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M: Richard Zhu <r65037@freescale.com>
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M: Lucas Stach <l.stach@pengutronix.de>
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@ -91,4 +91,12 @@ config PCI_XGENE
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There are 5 internal PCIe ports available. Each port is GEN3 capable
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and have varied lanes from x1 to x8.
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config PCI_LAYERSCAPE
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bool "Freescale Layerscape PCIe controller"
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depends on OF && ARM
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select PCIE_DW
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select MFD_SYSCON
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help
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Say Y here if you want PCIe controller support on Layerscape SoCs.
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endmenu
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@ -11,3 +11,4 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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179
drivers/pci/host/pci-layerscape.c
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drivers/pci/host/pci-layerscape.c
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/*
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* PCIe host controller driver for Freescale Layerscape SoCs
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*
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* Copyright (C) 2014 Freescale Semiconductor.
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*
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* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pcie-designware.h"
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/* PEX1/2 Misc Ports Status Register */
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#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
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#define LTSSM_STATE_SHIFT 20
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#define LTSSM_STATE_MASK 0x3f
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#define LTSSM_PCIE_L0 0x11 /* L0 state */
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/* Symbol Timer Register and Filter Mask Register 1 */
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#define PCIE_STRFMR1 0x71c
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struct ls_pcie {
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struct list_head node;
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struct device *dev;
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struct pci_bus *bus;
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void __iomem *dbi;
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struct regmap *scfg;
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struct pcie_port pp;
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int index;
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int msi_irq;
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};
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#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
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static int ls_pcie_link_up(struct pcie_port *pp)
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{
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u32 state;
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struct ls_pcie *pcie = to_ls_pcie(pp);
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regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
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state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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static void ls_pcie_host_init(struct pcie_port *pp)
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{
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struct ls_pcie *pcie = to_ls_pcie(pp);
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int count = 0;
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u32 val;
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dw_pcie_setup_rc(pp);
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while (!ls_pcie_link_up(pp)) {
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usleep_range(100, 1000);
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count++;
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if (count >= 200) {
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dev_err(pp->dev, "phy link never came up\n");
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return;
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}
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}
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/*
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* LS1021A Workaround for internal TKT228622
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* to fix the INTx hang issue
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*/
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val = ioread32(pcie->dbi + PCIE_STRFMR1);
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val &= 0xffff;
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iowrite32(val, pcie->dbi + PCIE_STRFMR1);
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}
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static struct pcie_host_ops ls_pcie_host_ops = {
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.link_up = ls_pcie_link_up,
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.host_init = ls_pcie_host_init,
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};
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static int ls_add_pcie_port(struct ls_pcie *pcie)
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{
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struct pcie_port *pp;
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int ret;
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pp = &pcie->pp;
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pp->dev = pcie->dev;
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pp->dbi_base = pcie->dbi;
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pp->root_bus_nr = -1;
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pp->ops = &ls_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(pp->dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int __init ls_pcie_probe(struct platform_device *pdev)
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{
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struct ls_pcie *pcie;
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struct resource *dbi_base;
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u32 index[2];
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int ret;
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pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie->dev = &pdev->dev;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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if (!dbi_base) {
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dev_err(&pdev->dev, "missing *regs* space\n");
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return -ENODEV;
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}
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pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
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if (IS_ERR(pcie->dbi))
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return PTR_ERR(pcie->dbi);
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pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"fsl,pcie-scfg");
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if (IS_ERR(pcie->scfg)) {
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dev_err(&pdev->dev, "No syscfg phandle specified\n");
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return PTR_ERR(pcie->scfg);
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}
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ret = of_property_read_u32_array(pdev->dev.of_node,
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"fsl,pcie-scfg", index, 2);
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if (ret)
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return ret;
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pcie->index = index[1];
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ret = ls_add_pcie_port(pcie);
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if (ret < 0)
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return ret;
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platform_set_drvdata(pdev, pcie);
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return 0;
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}
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1021a-pcie" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
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static struct platform_driver ls_pcie_driver = {
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.driver = {
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.name = "layerscape-pcie",
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.owner = THIS_MODULE,
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.of_match_table = ls_pcie_of_match,
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},
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};
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module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
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MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
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MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
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MODULE_LICENSE("GPL v2");
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