Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "This contains one i915 patch twice, as I merged it locally for testing, and then pulled some stuff in on top, and then Jani sent to me, I didn't think it was worth redoing all the merges of what I had tested. Summary: - amdgpu/radeon fixes for some more power management and VM races. - Two i915 fixes, one for the a recent regression, one another power management fix for skylake. - Two tegra dma mask fixes for a regression. - One ast fix for a typo I made transcribing the userspace driver, that I'd like to get into stable so I don't forget about it" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: gpu: host1x: Set DMA ops on device creation gpu: host1x: Set DMA mask drm/amdgpu: return from atombios_dp_get_dpcd only when error drm/amdgpu/cz: remove commented out call to enable vce pg drm/amdgpu/powerplay/cz: enable/disable vce dpm independent of vce pg drm/amdgpu/cz: enable/disable vce dpm even if vce pg is disabled drm/amdgpu/gfx8: specify which engine to wait before vm flush drm/amdgpu: apply gfx_v8 fixes to gfx_v7 as well drm/amd/powerplay: send event to notify powerplay all modules are initialized. drm/amd/powerplay: export AMD_PP_EVENT_COMPLETE_INIT task to amdgpu. drm/radeon/pm: update current crtc info after setting the powerstate drm/amdgpu/pm: update current crtc info after setting the powerstate drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM) drm/i915/skl: Fix power domain suspend sequence drm/ast: Fix incorrect register check for DRAM width drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
This commit is contained in:
commit
638c201e3f
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@ -77,7 +77,7 @@ void amdgpu_connector_hotplug(struct drm_connector *connector)
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} else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
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/* Don't try to start link training before we
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* have the dpcd */
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if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
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if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
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return;
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/* set it to OFF so that drm_helper_connector_dpms()
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@ -649,9 +649,6 @@ force:
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/* update display watermarks based on new power state */
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amdgpu_display_bandwidth_update(adev);
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adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
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adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
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/* wait for the rings to drain */
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for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
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struct amdgpu_ring *ring = adev->rings[i];
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@ -670,6 +667,9 @@ force:
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/* update displays */
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amdgpu_dpm_display_configuration_changed(adev);
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adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
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adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
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if (adev->pm.funcs->force_performance_level) {
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if (adev->pm.dpm.thermal_active) {
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enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
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@ -143,8 +143,10 @@ static int amdgpu_pp_late_init(void *handle)
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adev->powerplay.pp_handle);
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#ifdef CONFIG_DRM_AMD_POWERPLAY
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if (adev->pp_enabled)
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if (adev->pp_enabled) {
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amdgpu_pm_sysfs_init(adev);
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amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
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}
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#endif
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return ret;
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}
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@ -2202,8 +2202,7 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
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AMD_PG_STATE_GATE);
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cz_enable_vce_dpm(adev, false);
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/* TODO: to figure out why vce can't be poweroff. */
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/* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
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cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF);
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pi->vce_power_gated = true;
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} else {
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cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
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@ -2226,10 +2225,8 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
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}
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} else { /*pi->caps_vce_pg*/
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cz_update_vce_dpm(adev);
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cz_enable_vce_dpm(adev, true);
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cz_enable_vce_dpm(adev, !gate);
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}
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return;
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}
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const struct amd_ip_funcs cz_dpm_ip_funcs = {
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@ -3628,6 +3628,19 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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{
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int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
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uint32_t seq = ring->fence_drv.sync_seq;
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uint64_t addr = ring->fence_drv.gpu_addr;
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amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
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amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
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WAIT_REG_MEM_FUNCTION(3) | /* equal */
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WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
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amdgpu_ring_write(ring, addr & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
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amdgpu_ring_write(ring, seq);
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amdgpu_ring_write(ring, 0xffffffff);
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amdgpu_ring_write(ring, 4); /* poll interval */
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if (usepfp) {
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/* synce CE with ME to prevent CE fetch CEIB before context switch done */
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amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
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@ -4809,7 +4809,8 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
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amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
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WAIT_REG_MEM_FUNCTION(3))); /* equal */
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WAIT_REG_MEM_FUNCTION(3) | /* equal */
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WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
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amdgpu_ring_write(ring, addr & 0xfffffffc);
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amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
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amdgpu_ring_write(ring, seq);
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@ -402,8 +402,11 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,
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data.requested_ui_label = power_state_convert(ps);
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ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
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break;
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}
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break;
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case AMD_PP_EVENT_COMPLETE_INIT:
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ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
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break;
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default:
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break;
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}
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@ -165,6 +165,7 @@ const struct action_chain resume_action_chain = {
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};
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static const pem_event_action *complete_init_event[] = {
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unblock_adjust_power_state_tasks,
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adjust_power_state_tasks,
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enable_gfx_clock_gating_tasks,
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enable_gfx_voltage_island_power_gating_tasks,
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@ -226,7 +226,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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}
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} else {
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cz_dpm_update_vce_dpm(hwmgr);
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cz_enable_disable_vce_dpm(hwmgr, true);
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cz_enable_disable_vce_dpm(hwmgr, !bgate);
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return 0;
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}
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@ -227,7 +227,7 @@ static int ast_get_dram_info(struct drm_device *dev)
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} while (ast_read32(ast, 0x10000) != 0x01);
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data = ast_read32(ast, 0x10004);
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if (data & 0x400)
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if (data & 0x40)
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ast->dram_bus_width = 16;
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else
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ast->dram_bus_width = 32;
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@ -2303,15 +2303,15 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
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*/
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void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
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{
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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skl_display_core_uninit(dev_priv);
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/*
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* Even if power well support was disabled we still want to disable
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* power wells while we are system suspended.
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*/
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if (!i915.disable_power_well)
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intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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skl_display_core_uninit(dev_priv);
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}
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/**
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@ -2349,22 +2349,20 @@ bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
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{
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struct drm_device *dev = dev_priv->dev;
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struct device *device = &dev->pdev->dev;
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int ret;
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if (!IS_ENABLED(CONFIG_PM))
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return true;
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if (IS_ENABLED(CONFIG_PM)) {
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int ret = pm_runtime_get_if_in_use(device);
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ret = pm_runtime_get_if_in_use(device);
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/*
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* In cases runtime PM is disabled by the RPM core and we get an
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* -EINVAL return value we are not supposed to call this function,
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* since the power state is undefined. This applies atm to the
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* late/early system suspend/resume handlers.
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*/
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WARN_ON_ONCE(ret < 0);
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if (ret <= 0)
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return false;
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/*
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* In cases runtime PM is disabled by the RPM core and we get
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* an -EINVAL return value we are not supposed to call this
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* function, since the power state is undefined. This applies
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* atm to the late/early system suspend/resume handlers.
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*/
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WARN_ON_ONCE(ret < 0);
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if (ret <= 0)
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return false;
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}
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atomic_inc(&dev_priv->pm.wakeref_count);
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assert_rpm_wakelock_held(dev_priv);
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@ -1080,10 +1080,6 @@ force:
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/* update display watermarks based on new power state */
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radeon_bandwidth_update(rdev);
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rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
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rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
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rdev->pm.dpm.single_display = single_display;
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/* wait for the rings to drain */
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for (i = 0; i < RADEON_NUM_RINGS; i++) {
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struct radeon_ring *ring = &rdev->ring[i];
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/* update displays */
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radeon_dpm_display_configuration_changed(rdev);
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rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
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rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
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rdev->pm.dpm.single_display = single_display;
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if (rdev->asic->dpm.force_performance_level) {
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if (rdev->pm.dpm.thermal_active) {
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enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
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@ -18,6 +18,7 @@
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#include <linux/host1x.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/of_device.h>
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#include "bus.h"
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#include "dev.h"
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device->dev.coherent_dma_mask = host1x->dev->coherent_dma_mask;
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device->dev.dma_mask = &device->dev.coherent_dma_mask;
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dev_set_name(&device->dev, "%s", driver->driver.name);
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of_dma_configure(&device->dev, host1x->dev->of_node);
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device->dev.release = host1x_device_release;
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device->dev.bus = &host1x_bus_type;
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device->dev.parent = host1x->dev;
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@ -23,6 +23,7 @@
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#define CREATE_TRACE_POINTS
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#include <trace/events/host1x.h>
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.nb_bases = 8,
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.init = host1x01_init,
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.sync_offset = 0x3000,
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.dma_mask = DMA_BIT_MASK(32),
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};
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static const struct host1x_info host1x02_info = {
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.nb_bases = 12,
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.init = host1x02_init,
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.sync_offset = 0x3000,
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.dma_mask = DMA_BIT_MASK(32),
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};
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static const struct host1x_info host1x04_info = {
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.nb_bases = 64,
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.init = host1x04_init,
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.sync_offset = 0x2100,
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.dma_mask = DMA_BIT_MASK(34),
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};
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static const struct host1x_info host1x05_info = {
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@ -95,6 +99,7 @@ static const struct host1x_info host1x05_info = {
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.nb_bases = 64,
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.init = host1x05_init,
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.sync_offset = 0x2100,
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.dma_mask = DMA_BIT_MASK(34),
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};
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static struct of_device_id host1x_of_match[] = {
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@ -148,6 +153,8 @@ static int host1x_probe(struct platform_device *pdev)
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if (IS_ERR(host->regs))
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return PTR_ERR(host->regs);
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dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
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if (host->info->init) {
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err = host->info->init(host);
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if (err)
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@ -96,6 +96,7 @@ struct host1x_info {
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int nb_mlocks; /* host1x: number of mlocks */
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int (*init)(struct host1x *); /* initialize per SoC ops */
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int sync_offset;
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u64 dma_mask; /* mask of addressable memory */
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};
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struct host1x {
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Loading…
Reference in a new issue