arch/tile: enhance existing finv_buffer_remote() routine
It now takes an additional argument so it can be used to flush-and-invalidate pages that are cached using hash-for-home as well those that are cached with coherence point on a single cpu. This allows it to be used more widely for changing the coherence point of arbitrary pages when necessary. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>wifi-calibration
Chris Metcalf
parent
3cebbafd28
commit
63b7ca6b04
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@ -138,55 +138,12 @@ static inline void finv_buffer(void *buffer, size_t size)
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}
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/*
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* Flush & invalidate a VA range that is homed remotely on a single core,
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* waiting until the memory controller holds the flushed values.
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* Flush and invalidate a VA range that is homed remotely, waiting
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* until the memory controller holds the flushed values. If "hfh" is
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* true, we will do a more expensive flush involving additional loads
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* to make sure we have touched all the possible home cpus of a buffer
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* that is homed with "hash for home".
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*/
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static inline void finv_buffer_remote(void *buffer, size_t size)
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{
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char *p;
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int i;
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/*
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* Flush and invalidate the buffer out of the local L1/L2
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* and request the home cache to flush and invalidate as well.
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*/
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__finv_buffer(buffer, size);
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/*
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* Wait for the home cache to acknowledge that it has processed
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* all the flush-and-invalidate requests. This does not mean
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* that the flushed data has reached the memory controller yet,
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* but it does mean the home cache is processing the flushes.
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*/
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__insn_mf();
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/*
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* Issue a load to the last cache line, which can't complete
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* until all the previously-issued flushes to the same memory
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* controller have also completed. If we weren't striping
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* memory, that one load would be sufficient, but since we may
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* be, we also need to back up to the last load issued to
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* another memory controller, which would be the point where
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* we crossed an 8KB boundary (the granularity of striping
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* across memory controllers). Keep backing up and doing this
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* until we are before the beginning of the buffer, or have
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* hit all the controllers.
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*/
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for (i = 0, p = (char *)buffer + size - 1;
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i < (1 << CHIP_LOG_NUM_MSHIMS()) && p >= (char *)buffer;
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++i) {
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const unsigned long STRIPE_WIDTH = 8192;
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/* Force a load instruction to issue. */
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*(volatile char *)p;
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/* Jump to end of previous stripe. */
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p -= STRIPE_WIDTH;
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p = (char *)((unsigned long)p | (STRIPE_WIDTH - 1));
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}
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/* Wait for the loads (and thus flushes) to have completed. */
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__insn_mf();
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}
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void finv_buffer_remote(void *buffer, size_t size, int hfh);
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#endif /* _ASM_TILE_CACHEFLUSH_H */
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@ -21,3 +21,105 @@ void __flush_icache_range(unsigned long start, unsigned long end)
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{
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invalidate_icache((const void *)start, end - start, PAGE_SIZE);
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}
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/* Force a load instruction to issue. */
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static inline void force_load(char *p)
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{
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*(volatile char *)p;
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}
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/*
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* Flush and invalidate a VA range that is homed remotely on a single
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* core (if "!hfh") or homed via hash-for-home (if "hfh"), waiting
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* until the memory controller holds the flushed values.
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*/
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void finv_buffer_remote(void *buffer, size_t size, int hfh)
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{
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char *p, *base;
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size_t step_size, load_count;
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const unsigned long STRIPE_WIDTH = 8192;
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/*
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* Flush and invalidate the buffer out of the local L1/L2
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* and request the home cache to flush and invalidate as well.
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*/
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__finv_buffer(buffer, size);
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/*
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* Wait for the home cache to acknowledge that it has processed
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* all the flush-and-invalidate requests. This does not mean
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* that the flushed data has reached the memory controller yet,
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* but it does mean the home cache is processing the flushes.
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*/
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__insn_mf();
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/*
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* Issue a load to the last cache line, which can't complete
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* until all the previously-issued flushes to the same memory
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* controller have also completed. If we weren't striping
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* memory, that one load would be sufficient, but since we may
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* be, we also need to back up to the last load issued to
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* another memory controller, which would be the point where
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* we crossed an 8KB boundary (the granularity of striping
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* across memory controllers). Keep backing up and doing this
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* until we are before the beginning of the buffer, or have
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* hit all the controllers.
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*
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* If we are flushing a hash-for-home buffer, it's even worse.
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* Each line may be homed on a different tile, and each tile
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* may have up to four lines that are on different
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* controllers. So as we walk backwards, we have to touch
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* enough cache lines to satisfy these constraints. In
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* practice this ends up being close enough to "load from
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* every cache line on a full memory stripe on each
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* controller" that we simply do that, to simplify the logic.
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*
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* FIXME: See bug 9535 for some issues with this code.
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*/
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if (hfh) {
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step_size = L2_CACHE_BYTES;
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load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) *
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(1 << CHIP_LOG_NUM_MSHIMS());
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} else {
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step_size = STRIPE_WIDTH;
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load_count = (1 << CHIP_LOG_NUM_MSHIMS());
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}
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/* Load the last byte of the buffer. */
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p = (char *)buffer + size - 1;
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force_load(p);
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/* Bump down to the end of the previous stripe or cache line. */
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p -= step_size;
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p = (char *)((unsigned long)p | (step_size - 1));
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/* Figure out how far back we need to go. */
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base = p - (step_size * (load_count - 2));
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if ((long)base < (long)buffer)
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base = buffer;
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/*
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* Fire all the loads we need. The MAF only has eight entries
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* so we can have at most eight outstanding loads, so we
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* unroll by that amount.
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*/
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#pragma unroll 8
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for (; p >= base; p -= step_size)
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force_load(p);
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/*
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* Repeat, but with inv's instead of loads, to get rid of the
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* data we just loaded into our own cache and the old home L3.
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* No need to unroll since inv's don't target a register.
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*/
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p = (char *)buffer + size - 1;
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__insn_inv(p);
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p -= step_size;
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p = (char *)((unsigned long)p | (step_size - 1));
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for (; p >= base; p -= step_size)
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__insn_inv(p);
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/* Wait for the load+inv's (and thus finvs) to have completed. */
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__insn_mf();
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}
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@ -179,23 +179,46 @@ void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
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panic("Unsafe to continue.");
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}
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void flush_remote_page(struct page *page, int order)
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{
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int i, pages = (1 << order);
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for (i = 0; i < pages; ++i, ++page) {
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void *p = kmap_atomic(page);
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int hfh = 0;
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int home = page_home(page);
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#if CHIP_HAS_CBOX_HOME_MAP()
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if (home == PAGE_HOME_HASH)
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hfh = 1;
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else
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#endif
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BUG_ON(home < 0 || home >= NR_CPUS);
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finv_buffer_remote(p, PAGE_SIZE, hfh);
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kunmap_atomic(p);
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}
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}
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void homecache_evict(const struct cpumask *mask)
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{
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flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
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}
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/* Return a mask of the cpus whose caches currently own these pages. */
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static void homecache_mask(struct page *page, int pages,
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struct cpumask *home_mask)
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/*
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* Return a mask of the cpus whose caches currently own these pages.
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* The return value is whether the pages are all coherently cached
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* (i.e. none are immutable, incoherent, or uncached).
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*/
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static int homecache_mask(struct page *page, int pages,
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struct cpumask *home_mask)
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{
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int i;
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int cached_coherently = 1;
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cpumask_clear(home_mask);
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for (i = 0; i < pages; ++i) {
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int home = page_home(&page[i]);
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if (home == PAGE_HOME_IMMUTABLE ||
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home == PAGE_HOME_INCOHERENT) {
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cpumask_copy(home_mask, cpu_possible_mask);
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return;
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return 0;
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}
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#if CHIP_HAS_CBOX_HOME_MAP()
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if (home == PAGE_HOME_HASH) {
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@ -203,11 +226,14 @@ static void homecache_mask(struct page *page, int pages,
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continue;
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}
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#endif
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if (home == PAGE_HOME_UNCACHED)
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if (home == PAGE_HOME_UNCACHED) {
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cached_coherently = 0;
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continue;
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}
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BUG_ON(home < 0 || home >= NR_CPUS);
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cpumask_set_cpu(home, home_mask);
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}
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return cached_coherently;
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}
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/*
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@ -1620,7 +1620,7 @@ static unsigned int tile_net_tx_frags(lepp_frag_t *frags,
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if (b_len != 0) {
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if (!hash_default)
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finv_buffer_remote(b_data, b_len);
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finv_buffer_remote(b_data, b_len, 0);
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cpa = __pa(b_data);
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frags[n].cpa_lo = cpa;
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@ -1643,7 +1643,7 @@ static unsigned int tile_net_tx_frags(lepp_frag_t *frags,
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if (!hash_default) {
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void *va = pfn_to_kaddr(pfn) + f->page_offset;
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BUG_ON(PageHighMem(f->page));
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finv_buffer_remote(va, f->size);
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finv_buffer_remote(va, f->size, 0);
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}
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cpa = ((phys_addr_t)pfn << PAGE_SHIFT) + f->page_offset;
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